A
Analog_Guy
Guest
I generally implement resets with asynchronous assertion and
synchronous de-assertion. With a single reset, this is simple.
However, what happens if there are multiple reset inputs but I only
want one internal reset?
I was always under the impression that one should not have any
combinational logic in the asynchronous reset path, as it could lead
to static hazards (and reset glitches). So, how do you combine two
resets into one without using combinational logic somewhere?
I was thinking of two scenarios:
1. AND the two resets coming into the FPGA, and connect to the
asynchronous reset of a synchronizer. The output of the synchronizer
is the single internal reset.
2. Individually synchronize the two resets coming into the FPGA (note
that each reset input feeds the asynchronous reset of the
synchronizer). AND the output of each of the synchronizers and feed
this single signal into the asynchronous reset of a final flip-flop.
The output of this flip-flop is the single internal reset.
In both cases we achieve asynchronous assertion and synchronous de-
assertion ... however, in both cases there is combinational logic in
the asynchronous reset path.
Any suggestions how these multiple resets should be combined?
synchronous de-assertion. With a single reset, this is simple.
However, what happens if there are multiple reset inputs but I only
want one internal reset?
I was always under the impression that one should not have any
combinational logic in the asynchronous reset path, as it could lead
to static hazards (and reset glitches). So, how do you combine two
resets into one without using combinational logic somewhere?
I was thinking of two scenarios:
1. AND the two resets coming into the FPGA, and connect to the
asynchronous reset of a synchronizer. The output of the synchronizer
is the single internal reset.
2. Individually synchronize the two resets coming into the FPGA (note
that each reset input feeds the asynchronous reset of the
synchronizer). AND the output of each of the synchronizers and feed
this single signal into the asynchronous reset of a final flip-flop.
The output of this flip-flop is the single internal reset.
In both cases we achieve asynchronous assertion and synchronous de-
assertion ... however, in both cases there is combinational logic in
the asynchronous reset path.
Any suggestions how these multiple resets should be combined?