Multiple related clocks in Verilog?

[Tobias Weingartner]

Hello all,

I've got a design in Verilog that seems to work (yippie), synthesises
into xc2s50 (is that right, spartan-II, "50" size), and according to
the ISE 6.1 should clock at a nifty 110MHz or so. In order to make it
clock this fast (original was ~85MHz), I had to clock 2 registers on the
"opposite" edge of the only clock I am using.

Now, with some further analysis, it seems that I could get a further
speedup using 2 clocks. The "master" clock, and a "slave" clock some
270 degrees "later" in the cycle. Analysing the design shows me that
I would be able to reduce the total cycle time further, likely getting
close to 150MHz.

However, the problem I have is, how do I let ISE know about such clocks?
Such that it can optimize for them, and know that they are related, and
the manner in which they are related?

--
[100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

 

[gabor]

This isn't really a Verilog question. You need to do this in the UCF
file.
I have an example of using two clocks. In this case they are related
but with
different frequencies. Use the FROM:TO time spec to indicate the time
allowed for signals to propagate from one clock domain to the other
like:

NET "fpga_sysclkb" period = 15 ns ;
NET "pico_clk" period = 30 ns ;
NET "fpga_sysclkb" TNM="FastFlops";
NET "pico_clk" TNM="SlowFlops";
TIMESPEC "TS_fastslow"=FROM "SlowFlops" TO "FastFlops" 15 ns;
NET "pico_proc/instruction*" TIG=TS_fastslow;

Here I'm restricting signals from the "slow" clock domain to have only
15 ns (half the slow clock period) when moving to the "fast" clock
domain.
If you run the clocks at the same frequency your timespec would
probably
just be the delay from the rising edge of one clock to the rising edge
of the
other. Then I tell ISE to ignore the 15 nS spec for certain signals
using
TIG. The more general usage of TIG would also cancel the period spec
for these signals so here I specify TIG=TS_fastslow to only ignore the
clock to clock time spec and not the pico_clk perios spec.

If you use a DLL to generate clocks, you may find that ISE
automatically
calculates the timing relationships if you give the input clock a
period spec.

Hope this helps...

Tobias Weingartner wrote:

Hello all,

I've got a design in Verilog that seems to work (yippie), synthesises
into xc2s50 (is that right, spartan-II, "50" size), and according to
the ISE 6.1 should clock at a nifty 110MHz or so. In order to make it
clock this fast (original was ~85MHz), I had to clock 2 registers on the
"opposite" edge of the only clock I am using.

Now, with some further analysis, it seems that I could get a further
speedup using 2 clocks. The "master" clock, and a "slave" clock some
270 degrees "later" in the cycle. Analysing the design shows me that
I would be able to reduce the total cycle time further, likely getting
close to 150MHz.

However, the problem I have is, how do I let ISE know about such clocks?
Such that it can optimize for them, and know that they are related, and
the manner in which they are related?

--
[100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax