C
CADillac
Guest
Hi
I have multiple ground in a RF environment. They get shorted through
the substrate with the ptie. I have to create a PSUB2 layer to put
around these multiple power blocks to isolate the sub around a
particular transistor to prevent LVS shorting. What is the simplest
"logic" for such a code ( in Calibre or Assura )that I can add to a
existing deck without disturbing it too much...This question has
probably been asked many time but I cannot find it in the archive... i
appreciate your resposnse.
Best regards
I have multiple ground in a RF environment. They get shorted through
the substrate with the ptie. I have to create a PSUB2 layer to put
around these multiple power blocks to isolate the sub around a
particular transistor to prevent LVS shorting. What is the simplest
"logic" for such a code ( in Calibre or Assura )that I can add to a
existing deck without disturbing it too much...This question has
probably been asked many time but I cannot find it in the archive... i
appreciate your resposnse.
Best regards