Multiple Mux instances by parameter.

[Roy]

Hi All.

I am trying to create a synthesizeable module which get a parameter
and according to it determines the number of muxes in the design. for
example:

for parameter =3 I will get the following:

assign out[0] = input_signal;
assign out[1] = (en[0] ? in[0] : out[0]);
assign out[2] = (en[1] ? in[1] : out[1]);

for parameter =4 :

assign out[0] = input_signal;
assign out[1] = (en[0] ? in[0] : out[0]);
assign out[2] = (en[1] ? in[1] : out[1]);
assign out[3] = (en[2] ? in[2] : out[2]);

for parameter 5,6,7 ... etc.

Any help will be appreciated.

Thanks
Roy

 

[Mark Curry]

Roy wrote:

Hi All.

I am trying to create a synthesizeable module which get a parameter
and according to it determines the number of muxes in the design. for
example:

for parameter =3 I will get the following:

assign out[0] = input_signal;
assign out[1] = (en[0] ? in[0] : out[0]);
assign out[2] = (en[1] ? in[1] : out[1]);

for parameter =4 :

assign out[0] = input_signal;
assign out[1] = (en[0] ? in[0] : out[0]);
assign out[2] = (en[1] ? in[1] : out[1]);
assign out[3] = (en[2] ? in[2] : out[2]);

for parameter 5,6,7 ... etc.

Think of the boolean equivalent of a mux, and it's
easier:

module mux_shift( input_signal, in, en, out );
parameter
width = 4;

input input_signal;
input [ ( width - 2 ) : 0 ] in;
input [ ( width - 2 ) : 0 ] en;
output [ ( width - 1 ) : 0 ] out;

// Notice constant enable for bit zero
wire [ ( width - 1 ) : 0 ] en_shifted = { en, 1'b1 };

wire [ ( width - 1 ) : 0 ] in_shifted = { in, input_signal };

// lsb will be don't care
wire [ ( width - 1 ) : 0 ] out_shifted = out << 1;

// Create boolean equivalent of mux.
wire [ ( width - 1 ) : 0 ] out = ( ( en & in_shifted ) |
( ~en & out_shifted ) );

endmodule

Syntacticcally correct, but untested...

Regards,

Mark



--
Mark Curry
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[Steven Sharp]

royzem@yahoo.com (Roy) wrote in message news:<7fefa59.0310202247.4f7584c2@posting.google.com>...

I am trying to create a synthesizeable module which get a parameter
and according to it determines the number of muxes in the design. for
example:

for parameter =3 I will get the following:

assign out[0] = input_signal;
assign out[1] = (en[0] ? in[0] : out[0]);
assign out[2] = (en[1] ? in[1] : out[1]);

One possible solution is to use Verilog-2001 generates, but they are
not supported in all tools. Another solution would be to put one MUX
into a module and then use an array of instances of that module. But
some tools still don't support arrays of instances either.

The most portable solution is probably to use a single vector continuous
assignment to implement the entire set of muxes. Since there is not a
bitwise version of the conditional operator (?, the MUX would have to
be built with explicit bitwise AND and OR logic instead. Assuming a
parameter called WIDTH, this would look something like:

assign out[0] = input_signal;
assign out[WIDTH-1:1] = (en & in) | (~en & out[WIDTH-2:0]);

Note that this approach of using MUXES in series will have a propagation
delay proportional to the number of MUXES in series, which may cause you
problems. Assuming you are really trying to produce a MUX with WIDTH
inputs, and don't need the intermediate out values, you can do it in two
logic levels (though the second level needs WIDTH inputs, so it might
require multiple cascaded gates to implement).