multiple globals in LVS

Hi all,

I am currently putting together a chip which contains a number of
instances of a circuit core. The core uses global net names within it
(e.g. clk!). The problem is simple, in the layout the cores are
seperate and so the cores are within those blocks and not connected
from core to core (e.g. clk! in core 1 is not connected to clk! in
core 2). In the schematic, the netlister connects the globals in one
core to the globals in the other core (because they are globals...)
and complains that its not the same as the schematic.

I suppose what I am looking for is a way for the schematic netlister
not to use global net names above a certain hierarchy level.

Any advice would be greatly appreciated!

Thanks,

Reuben

 

[S. Badel]

I am currently putting together a chip which contains a number of
instances of a circuit core. The core uses global net names within it
(e.g. clk!). The problem is simple, in the layout the cores are
seperate and so the cores are within those blocks and not connected
from core to core (e.g. clk! in core 1 is not connected to clk! in
core 2). In the schematic, the netlister connects the globals in one
core to the globals in the other core (because they are globals...)
and complains that its not the same as the schematic.

The recommended way to handle such cases is to use inherited connections instead of plain global
signals. Inherited connections can be overridden at any level of hierarchy.

If your designs use inherited connections consistently, then you can simply add a netSet property on
each of the cores on the toplevel, to override the global connections with, say, clk_1, clk_2 and so on.

If your design doesn't use inherited connections, a quick search on sourcelink gave solution
#1843566, which includes SKILL code to change all the globals to inherited connections in a design.


Stéphane