Multiple event control statements

[Olivier lemaire]

Hi there,
I try to synthesize this code and that does not work. I don't understand...

module pulse_to_period(clk, in, out);
input clk, in;
output out;

wire in, clk;
reg out;

integer i;

always @(posedge in)
begin
out = 1'b1;
for (i = 0; i < 10 ; i = i + 1)
begin
@(negedge clk);
end
out = 1'b0;
end
endmodule

Anyone can help me, please.

Olivier

 

[Gabor]

Olivier lemaire wrote:

Hi there,
I try to synthesize this code and that does not work. I don't understand...

module pulse_to_period(clk, in, out);
input clk, in;
output out;

wire in, clk;
reg out;

integer i;

always @(posedge in)
begin
out = 1'b1;
for (i = 0; i < 10 ; i = i + 1)
begin
@(negedge clk);
end
out = 1'b0;
end
endmodule

Anyone can help me, please.

Olivier

Basically, the code you posted is asking the synthesizer to make a
flip-flop that gets set on the rising edge of one signal, and
cleared on the tenth subsequent falling edge of another signal.
Since such a flip-flop doesn't exist in real hardware, synthesis
gives you an error. You need to define your logic functionality
in terms that the synthesizer knows how to infer logic from.

I'm sure that your code simulated fine, and I see nothing wrong
with it for use in a test bench. However real hardware needs
to be built from available logic elements. If you want hardware
that behaves like the simulation, you need to have at a minimum
5 flip-flops - one that gets set on the rising edge of "in"
and cleared (asynchronously). The other four count to ten while
the first one is high. The state of those four needs to be decoded
to clear the first one (glitchlessly). It is possible to have
a glitchless decode when the count never exceeds the value you
are decoding.

HTH,
Gabor