multiple clocking block wait on event followed by assignment

Hi All;

Given the following interface definition

interface xx_if(input clk, output data);
clocking posedge_cb @(posedge clk);
endclocking
clocking negedge_cb @(negedge clk);
endclocking
clocking driver_cb @(posedge clk or negedge clk);
output #4ns data;
endclocking

modport driver_mp(clocking posedge_cb, clocking negedge_cb, clocking driver_cb);
endinterface

...
virtual xx_if.driver_mp m_if;

Can anyone tell me if the following statement is guaranteed to drive 'value' following the next posedge of the interface clock:

@(m_if.posedge_cb) m_if.driver_cb.data <= value;

i.e. there's no race condition where the @(m_if.posedge_cb) waits for the clk posedge, but then the assignment through the driver_cb, because it's a difference clocking block, waits for another full cycle of the clock?

Thanks,
Robert