MultiFileCompilationUnit and Precision Synthesis

"The IEEE P1800 Draft Standard for SystemVerilog requires that the
default behavior of the
vlog command is to treat each Verilog design file listed on the
command line as a separate
compilation unit."

But how to get this behaviour in Precision Synthesis (Lattice OEM
2007a9)?
It seems to treat all listed input files as one big file, opposing the
default behaviour of Modelsim and the draft standard and i found no
way changing it.