Multidimensional port.

[vssumesh]

Hello all
Is it possible to instantiate multi dimensional input/output port in
verilog2001.
I tried the following code.

module A(in,out);
input [7:0]in[7:0];
output [7:0]out[7:0];

but it did gave an error in the Xilinx ISE 6.2....

Sumesh

 

vssumesh wrote:

Is it possible to instantiate multi dimensional input/output port in
verilog2001.

No.

 

[Svilen]

If I remember correctly according to the System Verilog standard it
should be possible. I haven't seen it implemented yet. At least the
latest ncverilog is complaining about multidimentional ports (packed)
and multidimentional parameters.

Svilen

vssumesh wrote:

Hello all
Is it possible to instantiate multi dimensional input/output port in
verilog2001.
I tried the following code.

module A(in,out);
input [7:0]in[7:0];
output [7:0]out[7:0];

but it did gave an error in the Xilinx ISE 6.2....

Sumesh

 

[raul]

Hi,

Why don't you use 63:0 input/output ports and then read/write
individual bytes inside your module?

RAUL