Multidimensional generic vhdl

[Salman]

Hi,

I'm trying to create a generic mux that takes 2 parameters..such as
mux_2_2x1 or mux_8_8x1, etc

taking the form mux_A_Bx1

where the parameters would be A the width of the inputs and B the
number of inputs...and there always is 1 output....the problem is : how
do you have a parameterizable number of input ports and how do you code
this? Is something like this synthesizable?

Salman

 

[Mike Treseler]

Salman wrote:

I'm trying to create a generic mux that takes 2 parameters..such as
mux_2_2x1 or mux_8_8x1, etc
taking the form mux_A_Bx1
where the parameters would be A the width of the inputs and B the
number of inputs...and there always is 1 output....the problem is : how
do you have a parameterizable number of input ports and how do you code
this?

It's possible, but not necessary if you have quartus or ise.
Muxes will be inferred as needed from conditional statements.

Notice that the netlist here:
http://home.comcast.net/~mike_treseler/uart.pdf
has about 45 muxes of various sizes.

Notice that the source code here:
http://home.comcast.net/~mike_treseler/uart.vhd
that generated the netlist does not
even mention a mux.


-- Mike Treseler

 

[Andy]

Salman wrote:

Hi,

I'm trying to create a generic mux that takes 2 parameters..such as
mux_2_2x1 or mux_8_8x1, etc

taking the form mux_A_Bx1

where the parameters would be A the width of the inputs and B the
number of inputs...and there always is 1 output....the problem is : how
do you have a parameterizable number of input ports and how do you code
this? Is something like this synthesizable?

Salman

The only way I've seen it done is to have a single vector as the
input(s), and slice it up internally. I've changed b to be the number
of bits in the select line (2**b inputs)

generic (a, b ; natural);
port (input : in std_logic_vector(a * 2**b - 1 downto 0);
select : in std_logic(b - 1 downto 0);
output : out std_logic_vector(a - 1 downto 0));

There is a proposed update to vhdl to allow arrays of unconstrained
arrays, which would allow you to create a type that could be used for
the input port the way you envisioned it.

Andy

 

[Jim Lewis]

Salman,
Is this a homework problem? I will give you some
good hints either way.

Since this is a small simple block of combinational
logic, I would use a subprogram with unconstrained arrays
(to allow the width to adjust based on inputs) and
initialize the inputs (so if you don't use them they
default to 0). The only thing you need to constrain
is the multiplexor selector (case statement requires
a locally static type).

This approach will reduce your problem size to creating
mux2, mux4, mux8, ... If you truely want it flexible,
I would create it for std_logic and std_logic_vector.

Synthesis?
I have not tried initialized subprogram inputs on

enough synthesis tools yet to say it is portable
across synthesis tools, the rest though should
not be a problem.




Cheers,
Jim

Hi,

I'm trying to create a generic mux that takes 2 parameters..such as
mux_2_2x1 or mux_8_8x1, etc

taking the form mux_A_Bx1

where the parameters would be A the width of the inputs and B the
number of inputs...and there always is 1 output....the problem is : how
do you have a parameterizable number of input ports and how do you code
this? Is something like this synthesizable?

Salman

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
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