M
Michael
Guest
hello
I'm trying to implement a PCI bus, and i'm trying to interpret C/BE
for the number of words to be read.. what i have done is, to have one
process that "listens" for C/BE and interprets it, then in another
process, it decrements the count per read.. I get the multi source
error, because I can't modify the same signal in 2 processes.. How
else can I approach this? The following is my code:
counting: process(C_BE, AD)
begin
case DEV_RTYP is
when "0100" =>
count <= "010";
when "0101" =>
count <= "011";
when others =>
end case;
end process counting;
out_logic: process(current_state, DEV_DATA, DEV_ADDR, DEV_RTYP,
DEV_RDY, DEV_GRNT,
FRAME, C_BE, IRDY, TRDY, DEVSEL, AD)
begin
...
case current_state is
...
when "00011" =>
IRDY <= '1';
DRV_RDY <= '1';
DEV_DATA <= AD;
if LAST = '1' then
FRAME <= '0';
else
FRAME <= '1';
end if;
count <= count - 1;
...
end process out_logic;
please help
thank you
I'm trying to implement a PCI bus, and i'm trying to interpret C/BE
for the number of words to be read.. what i have done is, to have one
process that "listens" for C/BE and interprets it, then in another
process, it decrements the count per read.. I get the multi source
error, because I can't modify the same signal in 2 processes.. How
else can I approach this? The following is my code:
counting: process(C_BE, AD)
begin
case DEV_RTYP is
when "0100" =>
count <= "010";
when "0101" =>
count <= "011";
when others =>
end case;
end process counting;
out_logic: process(current_state, DEV_DATA, DEV_ADDR, DEV_RTYP,
DEV_RDY, DEV_GRNT,
FRAME, C_BE, IRDY, TRDY, DEVSEL, AD)
begin
...
case current_state is
...
when "00011" =>
IRDY <= '1';
DRV_RDY <= '1';
DEV_DATA <= AD;
if LAST = '1' then
FRAME <= '0';
else
FRAME <= '1';
end if;
count <= count - 1;
...
end process out_logic;
please help
thank you