S
sftchs
Guest
Any help is appreciated. I get multi-source errors on signals that ar
being driven by different states in the same FSM and I'm not sure why. Her
is one of the multi-source errors that I get:
"Multi-source in Unit <tst_1> on signal <ram<15><3>>; this signal i
connected to multiple drivers."
and here is the source for the entire unit
module tst_1(
input rst,
input clk,
output [7:0] led
);
parameter s_0 = 2'b00;
parameter s_1 = 2'b01;
parameter s_2 = 2'b10;
parameter s_3 = 2'b11;
reg [1:0] state;
reg [7:0] ram[0:15];
reg [7:0] regs[0:7];
initial begin
state <= s_0;
end
always @(posedge clk) begin
if (rst == 1'b1)
state <= s_0;
else begin
case (state)
s_0: begin
ram[15] <= 8'h00;
state <= s_1;
end
s_1: begin
regs[0] <= ~ram[8];
ram[15][0] <= 1'b1;
ram[15][1] <= 1'b0;
state <= s_2;
end
s_2: begin
ram[7] <= regs[0];
ram[15][2] <= ~regs[0][7];
ram[15][3] <= regs[0][3];
state <= s_3;
end
s_3: begin
ram[8] <= ram[7] ^ ram[15];
state <= s_1;
end
default:
state <= s_0;
endcase
end
end
assign led = regs[0];
endmodule
For the interested, I get multi-source errors on ram[15][3], ram[15][2]
and ram[15][0]... but not ram[15][1]. I'm sure this must be somethin
obvious to the well-trained.
---------------------------------------
Posted through http://www.FPGARelated.com
being driven by different states in the same FSM and I'm not sure why. Her
is one of the multi-source errors that I get:
"Multi-source in Unit <tst_1> on signal <ram<15><3>>; this signal i
connected to multiple drivers."
and here is the source for the entire unit
module tst_1(
input rst,
input clk,
output [7:0] led
);
parameter s_0 = 2'b00;
parameter s_1 = 2'b01;
parameter s_2 = 2'b10;
parameter s_3 = 2'b11;
reg [1:0] state;
reg [7:0] ram[0:15];
reg [7:0] regs[0:7];
initial begin
state <= s_0;
end
always @(posedge clk) begin
if (rst == 1'b1)
state <= s_0;
else begin
case (state)
s_0: begin
ram[15] <= 8'h00;
state <= s_1;
end
s_1: begin
regs[0] <= ~ram[8];
ram[15][0] <= 1'b1;
ram[15][1] <= 1'b0;
state <= s_2;
end
s_2: begin
ram[7] <= regs[0];
ram[15][2] <= ~regs[0][7];
ram[15][3] <= regs[0][3];
state <= s_3;
end
s_3: begin
ram[8] <= ram[7] ^ ram[15];
state <= s_1;
end
default:
state <= s_0;
endcase
end
end
assign led = regs[0];
endmodule
For the interested, I get multi-source errors on ram[15][3], ram[15][2]
and ram[15][0]... but not ram[15][1]. I'm sure this must be somethin
obvious to the well-trained.
---------------------------------------
Posted through http://www.FPGARelated.com