K
Kiran
Guest
Hi All,
I would like to start a discussion on multi-clock designs.
When a design has multiple unrelated clocks (unrelated in the sense
that the frequencies do not have an integer relationship), the clocks
are considered to be asynchronous. The design is partitioned into
separate clock domains and signals crossing these clock domains are
passed through synchronizers. The synchronizers are used to reduce
the chance of metastability. All these are standard design practices.
Lets take the case where there are two clocks. One is derived from the
other using a clock divider. Therefore the derived clock has half the
frequency of the master clock. Are these clocks still considered to
be asynchronous? Do we still have to use synchronizers on signals
crossing the clock domains even though we know the timing relationship
between these two clocks?
I encountered two sets of opinion.
1. They can be considered to be synchronous. There will be no problem
during clock tree synthesis. Its ok to use clock divider.
2. They still are asynchronous clocks. Design practices for
multi-clock designs still have to applied. Otherwise, clock tree
synthesis will be a problem. Timing closure will be a problem because
gate level timing simulation may not be sufficient, instead SPICE
simulations may have to be done. It is not ok to use clock divider.
Always use PLL to generate the clocks in the design.
Whats your opinion?
Regards,
Kiran.
I would like to start a discussion on multi-clock designs.
When a design has multiple unrelated clocks (unrelated in the sense
that the frequencies do not have an integer relationship), the clocks
are considered to be asynchronous. The design is partitioned into
separate clock domains and signals crossing these clock domains are
passed through synchronizers. The synchronizers are used to reduce
the chance of metastability. All these are standard design practices.
Lets take the case where there are two clocks. One is derived from the
other using a clock divider. Therefore the derived clock has half the
frequency of the master clock. Are these clocks still considered to
be asynchronous? Do we still have to use synchronizers on signals
crossing the clock domains even though we know the timing relationship
between these two clocks?
I encountered two sets of opinion.
1. They can be considered to be synchronous. There will be no problem
during clock tree synthesis. Its ok to use clock divider.
2. They still are asynchronous clocks. Design practices for
multi-clock designs still have to applied. Otherwise, clock tree
synthesis will be a problem. Timing closure will be a problem because
gate level timing simulation may not be sufficient, instead SPICE
simulations may have to be done. It is not ok to use clock divider.
Always use PLL to generate the clocks in the design.
Whats your opinion?
Regards,
Kiran.