F
Florian Schlembach
Guest
Hi there,
I am trying to implement a Xilinx IP Filter core (created with the FIR Compiler) using Multiple Channels on a Spartan-3A.
I want to feed the filter module with a certain sample rate (10 MHz), master clock is 100 MHz (so 10ns each cycle). So I need to put in one sample each 10 cycles. Since, I do have an I and Q component, I have chosen this filter module to process two channels in a time-multiplexed scheme which ends up in one sample each 5 cycles. An output pin of the filter, called CHAN_IN, signalizes me which signal and "rfd" when to feed in a sample which has to be indicated with a ND input flag signal.
The timing can be seen here:
http://upload-pictures.de/bild.php/22822,screenshot2PMBGJ.png
(taken from here,p.60, http://www.google.de/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&ved=0CDYQFjAA&url=http%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fip_documentation%2Ffir_compiler_ds534.pdf&ei=wNHuUMv5F9DEsgam3YGYCA&usg=AFQjCNHJm-Zj3p9Oi2eUByInfzHKyfws4g&bvm=bv.1357700187,d.Yms )
My code can be seen here: http://pastebin.com/0VvfNT1p
Now, the problem is that the filter only gives out sample each 12 cycles which is to slow to avoid an overflow. It might be because of the nonblocking statements in lines 74 and 76 which delays for another cycle, respectively..
Here is a screenshot where you can see the duration of 120ns what should be at 100ns: http://upload-pictures.de/bild.php/22823,screenshot3C5D5M.png
How can I fix that problem? Any advices for the Verilog code above?
Thanks
I am trying to implement a Xilinx IP Filter core (created with the FIR Compiler) using Multiple Channels on a Spartan-3A.
I want to feed the filter module with a certain sample rate (10 MHz), master clock is 100 MHz (so 10ns each cycle). So I need to put in one sample each 10 cycles. Since, I do have an I and Q component, I have chosen this filter module to process two channels in a time-multiplexed scheme which ends up in one sample each 5 cycles. An output pin of the filter, called CHAN_IN, signalizes me which signal and "rfd" when to feed in a sample which has to be indicated with a ND input flag signal.
The timing can be seen here:
http://upload-pictures.de/bild.php/22822,screenshot2PMBGJ.png
(taken from here,p.60, http://www.google.de/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&ved=0CDYQFjAA&url=http%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fip_documentation%2Ffir_compiler_ds534.pdf&ei=wNHuUMv5F9DEsgam3YGYCA&usg=AFQjCNHJm-Zj3p9Oi2eUByInfzHKyfws4g&bvm=bv.1357700187,d.Yms )
My code can be seen here: http://pastebin.com/0VvfNT1p
Now, the problem is that the filter only gives out sample each 12 cycles which is to slow to avoid an overflow. It might be because of the nonblocking statements in lines 74 and 76 which delays for another cycle, respectively..
Here is a screenshot where you can see the duration of 120ns what should be at 100ns: http://upload-pictures.de/bild.php/22823,screenshot3C5D5M.png
How can I fix that problem? Any advices for the Verilog code above?
Thanks