Mulptiple Driving in Processes, simulation problem.

[Alex]

Gentlemen,

I got stuck with what seems to be a simple problem of multiple driving.

I have to processes that update a common signal (it is for pure behaviour
simulations).
However during simulations in ModelSim 5.8SE the signal starts being
updated only after second process is activated
(see the example code below). Obviously if I split these processes into
different design units that will help, but what
am I missing to make it work (or simulated) properly in the way, as
follows???


ARCHITECTURE beh OF temp_test IS
signal x: std_logic;
BEGIN
set: process(s,x) is
begin
if s='1' then
x<='1' after 1 ps;
elsif (s='0' and x'event ) then
x<='Z' after 1 ps;
elsif (s='0' and x='X' ) then
x<='Z' after 1 ps;
end if;
end process;

reset: process(r,x) is
begin
if r='1' then
x<='0' after 1 ps;
elsif (r='0' and x'event ) then
x<='Z' after 1 ps;
elsif (r='0' and x='X' ) then
x<='Z' after 1 ps;
end if;
end process;
out<=x;

END ARCHITECTURE beh;

Thank you for help.


--
Alex

 

[Alex]

Problem solved. My mistake was that I didn't initialise the internal
signal, so
unactivated processes kept it as Undefined, and as a result of resolution
function
at the output was also Undefined.

Thanks.
Alex

Gentlemen,

I got stuck with what seems to be a simple problem of multiple driving.

I have to processes that update a common signal (it is for pure
behaviour simulations).
However during simulations in ModelSim 5.8SE the signal starts being
updated only after second process is activated
(see the example code below). Obviously if I split these processes into
different design units that will help, but what
am I missing to make it work (or simulated) properly in the way, as
follows???


ARCHITECTURE beh OF temp_test IS
signal x: std_logic;
BEGIN
set: process(s,x) is
begin
if s='1' then
x<='1' after 1 ps;
elsif (s='0' and x'event ) then
x<='Z' after 1 ps;
elsif (s='0' and x='X' ) then
x<='Z' after 1 ps;
end if;
end process;

reset: process(r,x) is
begin
if r='1' then
x<='0' after 1 ps;
elsif (r='0' and x'event ) then
x<='Z' after 1 ps;
elsif (r='0' and x='X' ) then
x<='Z' after 1 ps;
end if;
end process;
out<=x;

END ARCHITECTURE beh;

Thank you for help.

--
Alex

 

[Mike Treseler]

Alex wrote:

I got stuck with what seems to be a simple problem of multiple driving.

I have to processes that update a common signal (it is for pure
behaviour simulations).

http://groups.google.com/groups/search?q=process+shorts+%22outputs+together+%22

For simulation I use one process that
drives read-only signals like clk,
and a second process that uses
synchronous waits like:

wait until rising_edge(clk_s);

to drive and read all the other testbench wires.
See the testbench example here:

http://home.comcast.net/~mike_treseler/

-- Mike Treseler

 

[Alex]

Mike,

Yes, for testbenches I do exactly like you have mentioned. As I have said,
it is a pure behavioural
module, simply to test an IC circuits (in this particular case it is
charge storing), and parallel
assignment is done on purpose in order to trace hazards in circuit
functioning. It is possible to
do it by tracing test vectors as well, but I have decided to
do both .

Alex.

Alex wrote:

I got stuck with what seems to be a simple problem of multiple driving.
I have to processes that update a common signal (it is for pure
behaviour simulations).

http://groups.google.com/groups/search?q=process+shorts+%22outputs+together+%22

For simulation I use one process that
drives read-only signals like clk,
and a second process that uses
synchronous waits like:

wait until rising_edge(clk_s);

to drive and read all the other testbench wires.
See the testbench example here:

http://home.comcast.net/~mike_treseler/

-- Mike Treseler

--
Alex