mulitdimensional array at port configurations...

D

Dkthechamp

Guest
Hi,

How can we declare a multidimensional array, while declaring the port
of an entitity? (2 D in specific of std_logic_vector type). The input
is of 'x' bit each and there are n such inputs.

Thanks,

Deepak
 
Dkthechamp wrote:

Hi,

How can we declare a multidimensional array, while declaring the port
of an entitity? (2 D in specific of std_logic_vector type). The input
is of 'x' bit each and there are n such inputs.
Click to expand...
Put the type declaration in a package and make the contents of that package
visible for the entity. That is, put a use clause with that package (e.g.
use work.pkg.all;) in front of the entity declaration.

This of course implicates that the sizes of your multi dimensional array (or
alternatively, array of arrays or vectors) are fixed.

If you want them unconstrained, then the only solution is to use an
unconstrained one dimensional array (such as std_logic_vector) and do some
slicing magic in the architecture.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
 
On Tue, 24 Jul 2007 09:34:50 -0000,
Dkthechamp <dkthechamp@gmail.com> wrote:

How can we declare a multidimensional array, while declaring the port
of an entitity? (2 D in specific of std_logic_vector type). The input
is of 'x' bit each and there are n such inputs.
Click to expand...
In Verilog-2001, you can't.

Paul's post on packages is right for SystemVerilog.

If you don't have SystemVerilog tools, give up and use VHDL :)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On Jul 24, 12:41 pm, Paul Uiterlinden <puit...@notaimvalley.nl> wrote:
Dkthechamp wrote:
Hi,

How can we declare a multidimensional array, while declaring the port
of an entitity? (2 D in specific of std_logic_vector type). The input
is of 'x' bit each and there are n such inputs.

Put the type declaration in a package and make the contents of that package
visible for the entity. That is, put a use clause with that package (e.g.
use work.pkg.all;) in front of the entity declaration.

This of course implicates that the sizes of your multi dimensional array (or
alternatively, array of arrays or vectors) are fixed.

If you want them unconstrained, then the only solution is to use an
unconstrained one dimensional array (such as std_logic_vector) and do some
slicing magic in the architecture.

--
Paul Uiterlindenwww.aimvalley.nl
e-mail addres: remove the not.
Click to expand...
thanks Paul, will this solution be synthesizable !!!
 
On Jul 24, 1:44 pm, Dkthechamp <dkthech...@gmail.com> wrote:
On Jul 24, 12:41 pm, Paul Uiterlinden <puit...@notaimvalley.nl> wrote:



Dkthechamp wrote:
Hi,

How can we declare a multidimensional array, while declaring the port
of an entitity? (2 D in specific of std_logic_vector type). The input
is of 'x' bit each and there are n such inputs.

Put the type declaration in a package and make the contents of that package
visible for the entity. That is, put a use clause with that package (e.g.
use work.pkg.all;) in front of the entity declaration.

This of course implicates that the sizes of your multi dimensional array (or
alternatively, array of arrays or vectors) are fixed.

If you want them unconstrained, then the only solution is to use an
unconstrained one dimensional array (such as std_logic_vector) and do some
slicing magic in the architecture.

--
Paul Uiterlindenwww.aimvalley.nl
e-mail addres: remove the not.

thanks Paul, will this solution be synthesizable !!!
Click to expand...
i am using already using VHDL :)
 
On Tue, 24 Jul 2007 12:37:35 +0100, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> wrote:

If you don't have SystemVerilog tools, give up and use VHDL :)
Click to expand...
Oops, sincere apologies, wrong newsgroup ;-) Of course Paul is right
that in VHDL you need a package. A nasty case of typing at higher
speed than thinking.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On Jul 24, 7:03 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
On Tue, 24 Jul 2007 12:37:35 +0100, Jonathan Bromley

jonathan.brom...@MYCOMPANY.com> wrote:
If you don't have SystemVerilog tools, give up and use VHDL :)

If you can live with an array of arrays, the outer array can be
Click to expand...
unconstrained, the inner one must be constrained, in the current
version of vhdl. An advantage of arrays of arrays is that you can use
slices or elements of the outer array, and you can access slices or
elements of one element of the outer array. In a lot of hardware
circuit descriptions, this is very beneficial.

Usually when I define a type that is used in a port definition on an
entity, I put the package containing the type definition at the top of
the file for the entity. That way, if the entity is compiled, the
package is too, and both are visible (with the appropriate use
statement for the package).

In the future, generics on packages, and arrays of unconstrained
arrays will make this a lot more convenient.

Andy
 
Dkthechamp wrote:

Put the type declaration in a package and make the contents of that
package visible for the entity. That is, put a use clause with that
package (e.g. use work.pkg.all;) in front of the entity declaration.

This of course implicates that the sizes of your multi dimensional array
(or alternatively, array of arrays or vectors) are fixed.

If you want them unconstrained, then the only solution is to use an
unconstrained one dimensional array (such as std_logic_vector) and do
some slicing magic in the architecture.


thanks Paul, will this solution be synthesizable !!!
Click to expand...
As far as I know it is. The only problem perhaps is that it cannot not be
used at top level. But then again, this is unknown territory for me, as I
hardly ever bother with synthesis.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
 
Jonathan Bromley wrote:

Oops, sincere apologies, wrong newsgroup ;-) Of course Paul is right
that in VHDL you need a package. A nasty case of typing at higher
speed than thinking.
Click to expand...
It seems your brain is written in Verilog. The dead give away of course are
the race conditions! ;-)

Don't let that stop you posting though. The technical insights combined with
humor in your postings is a rare combination that I've grown to appreciate
very much.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
 
On Jul 25, 1:00 am, Paul Uiterlinden <puit...@notaimvalley.nl> wrote:
Dkthechamp wrote:
Put the type declaration in a package and make the contents of that
package visible for the entity. That is, put a use clause with that
package (e.g. use work.pkg.all;) in front of the entity declaration.

This of course implicates that the sizes of your multi dimensional array
(or alternatively, array of arrays or vectors) are fixed.

If you want them unconstrained, then the only solution is to use an
unconstrained one dimensional array (such as std_logic_vector) and do
some slicing magic in the architecture.

thanks Paul, will this solution be synthesizable !!!

As far as I know it is. The only problem perhaps is that it cannot not be
used at top level. But then again, this is unknown territory for me, as I
hardly ever bother with synthesis.

--
Paul Uiterlindenwww.aimvalley.nl
e-mail addres: remove the not.
Click to expand...
sir..
are arrays of vector synthesizeable????
just like if i declare something like
[7:0]temp [0:255] ?????
 
On Aug 7, 7:13 am, bullsandeagles <shanthan.chaki...@gmail.com> wrote:
On Jul 25, 1:00 am, Paul Uiterlinden <puit...@notaimvalley.nl> wrote:



Dkthechamp wrote:
Put the type declaration in a package and make the contents of that
package visible for the entity. That is, put a use clause with that
package (e.g. use work.pkg.all;) in front of the entity declaration.

This of course implicates that the sizes of your multi dimensional array
(or alternatively, array of arrays or vectors) are fixed.

If you want them unconstrained, then the only solution is to use an
unconstrained one dimensional array (such as std_logic_vector) and do
some slicing magic in the architecture.

thanks Paul, will this solution be synthesizable !!!

As far as I know it is. The only problem perhaps is that it cannot not be
used at top level. But then again, this is unknown territory for me, as I
hardly ever bother with synthesis.

--
Paul Uiterlindenwww.aimvalley.nl
e-mail addres: remove the not.

sir..
are arrays of vector synthesizeable????
just like if i declare something like
[7:0]temp [0:255] ?????
Click to expand...
Yes.

Andy
 
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