moving data from slower to faster clock domain

[vlsifresher]

Hi,

what is the best technique of moving data from a faster clock
domain(100 Mhz) to slower clock domain(75 Mhz)?

Pls guide me.

Thanks

 

[terabits]

If you are talking about data bus synchronisation, better go for data
buffers,
like two port access memory, read operates with one clock write with
another.
for control signals, use synchronizers.(not double buffering always)

Hi,

what is the best technique of moving data from a faster clock
domain(100 Mhz) to slower clock domain(75 Mhz)?

Pls guide me.

Thanks

 

You can design do this by using a synchronizer circuit. When moving
data from a fast clock to a slow clock, typically a FIFO is used.

Here's a link to a whitepaper that you can study on the Clock Domain
Crossing design and a software solution to verify the structure.

http://www.cadence.com/whitepapers/cdc_wp.pdf

- ay


On Feb 5, 10:37 am, "vlsifresher" <baj...@gmail.com> wrote:

Hi,

what is the best technique of moving data from a faster clock
domain(100 Mhz) to slower clock domain(75 Mhz)?

Pls guide me.

Thanks