Mosis padframes

[horridnoodle@hotmail.com]

I am planning to fab a chip with Mosis. I have a question about their
scalable cmos pad frames. I understand the reason behind scalable cmos
and it provides and easy conversion between feature sizes. I downloaded
the padframe for the AMIS C5 process, and I was wondering that since
the layout and padframe have different layers will the Metal 1 layer
and M1_pin layer be recognized as going together. Or is there some
conversion that is done to insure a good layout to pin interface.

Thanks