mos transistor modelling

hi,
I'm looking at modelling of the process variations in mos
transistor at say 90nm and below. I'm new to this group, and
not sure where exactly to post it.

Basically, the foundry guys give the standard deviation
data on vt, transconductance and Idss. With this I would like
to figure out how the (say)inverter delays are affected.
(Essentially try and figure out the distribution).

In my opinion, all the three are not totally uncorrelated
to each other. So, I presume selecting two of these should
do a good job. Is this on the right track??

And if someone has worked on these things can he/she share
some basic ideas with me??

ganesh

 

hi Kevin,
thanks for the information. But I'm actually looking for something
slightly different.
Its my mistake, since I didnt mention it clearly or rather not mention
it at all.

I'm looking at on chip variations. So, modelling the entire design at
SS or FF is too pessimistic.
So, within the same chip, vt etc of the transistors are going to vary.
I can take this into account if I do a statistical modelling (both at
SS and FF).
So, I get the delays as a probability distribution.

So, for a given value of vt, transconductance etc, I run spice and get
the delay.
Now, I vary these parameters accroding to some probability and get
various delays with various probabilities.
This way I can take care of on chip variations probabilistically.

Now, the issue is getting into the exact details of the modelling.
Every parameter vt, cgdo, cgso, gm, idss, AS, AD etc will vary. The
idea is to take uncorrelated parameters
as much as possible. Also if I take too many parameters, its difficult
to model.
So I would like to take some 2 or 3 dominant guys. I'm thinking of vt
and transconductance.
Are these choices ok??


ganesh

 

[Frank Moe]

Hi,
take about 10% of the worst case variation as the relative variation
across the chip as long as the chip is reasonably siced.
Frank