More Configuration Problems

[graeme.cunningham@googlem]

Configurations seem to be causing quite a few problems at the moment.
Could anyone help with mine?

I have an entity with two architectures and want my test bench to
instantiate and instance of each.

However both instances are being bound to the same architecture.

It seems just to be picking up the default configuration, as if I
reorder the the architectures in the file it "picks up" the last one to
be declared

I am using Active HDL 7.1


Thanks in advance.
Graeme

architecture TB of CKT_TB is
component comb_ckt is
port( input1: in std_logic;
input2: in std_logic;
input3: in std_logic;
output: out std_logic);
end component;

signal T_input1, T_input2, T_input3, T_output1, T_output2: std_logic;

begin

U_UT1: comb_ckt port map (T_input1,T_input2,T_input3,T_output1);
U_UT2: comb_ckt port map (T_input1,T_input2,T_input3,T_output2);

end TB;


configuration CFG_TB of CKT_TB is
for TB
for U_UT1: comb_ckt
use entity WORK.comb_ckt(behv);
end for;
for U_UT2: comb_ckt
use entity WORK.comb_ckt(struct);
end for;
end for;
end CFG_TB;

 

[Arnim]

I have an entity with two architectures and want my test bench to
instantiate and instance of each.

However both instances are being bound to the same architecture.

You tell the simulator to use cfg_tb as the top unit, don't you? If yes,
then your design should bind as expected.

It seems just to be picking up the default configuration, as if I
reorder the the architectures in the file it "picks up" the last one
to be declared

You're referring to the architectures of comb_ckt? This seems to me as
if the simulator uses default binding rules that select the most
recently analyzed architecture. You could check that the testbench
configuration is actually considered during elaboration.


Hope this helps

Arnim

 

[Andy]

Unless you want to be able to change the architecture binding of the
same instance between different simulations, you really don't need
components and/or configurations.

Simply directly instantiate the entity/architecture pair:

U_UT1: entity work.comb_ckt(behv) port map
(T_input1,T_input2,T_input3,T_output1);
U_UT2: entity work.comb_ckt(struct) port map
(T_input1,T_input2,T_input3,T_output2);

Note that this is a '93 standard feature, so you may have to tell your
tools to enable using them (some tools default to the '87 standard).

Andy