More about parameters?

B

Ben Heard

Guest
comp.lang.verilog,

In the thread "Is there a way to use generics in verilog?" the use of
parameters is mentioned. I believe that in VHDL it is possible to
override selected generics and leave the remaining as default; i.e. you
don't have to provide values for all generics if you only want to change
one.

Is there a way to do this in Verilog? For example

module Timing( Clock, Reset, Out );
parameter FastClockDiv = 4;
parameter SlowClockDiv = 16;
...

To instantiate with the defaults use

Timing T1( .Clock(A), .Reset(B), .Out(C) );

To instantiate overriding both parameters use

Timing #(5, 24) T1( .Clock(A), .Reset(B), .Out(C) );

How do I instantiate just overriding the FastClockDiv and leave
SlowClockDiv as the default from the module?

Thanks,
Ben
 
On Fri, 05 Sep 2003 09:30:20 -0400, Ben Heard <BenH@cipheroptics.com>
wrote:

comp.lang.verilog,

In the thread "Is there a way to use generics in verilog?" the use of
parameters is mentioned. I believe that in VHDL it is possible to
override selected generics and leave the remaining as default; i.e. you
don't have to provide values for all generics if you only want to change
one.

Is there a way to do this in Verilog? For example

module Timing( Clock, Reset, Out );
parameter FastClockDiv = 4;
parameter SlowClockDiv = 16;
...

To instantiate with the defaults use

Timing T1( .Clock(A), .Reset(B), .Out(C) );

To instantiate overriding both parameters use

Timing #(5, 24) T1( .Clock(A), .Reset(B), .Out(C) );

How do I instantiate just overriding the FastClockDiv and leave
SlowClockDiv as the default from the module?

Thanks,
Ben
Click to expand...
Timing #(5) T1( .Clock(A), .Reset(B), .Out(C) );

should override just fastclockdiv. But you can't just override
slowclockdiv by itself. V2001 supports parameter overrides by name I
believe.

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations
 
Hi Ben,
You do not have to provide value for SlowClockDiv. Leave it unmapped -
the default value will be used.

If you want to map only the second parameter you can use mapping by
name :
Timing #(.SlowClockDiv(24)) T1( .Clock(A), .Reset(B), .Out(C)
If your compilator doesn't support this construct (it's quite new
feature - introduced in verilog 2001 if I'm not wrong). You have no
choice - map default values to all the parameters before this one
which you intend to have non-default value.

HTH,
Marcin

Ben Heard <BenH@cipheroptics.com> wrote in message news:<3f588fed@btitelecom.net>...
comp.lang.verilog,

In the thread "Is there a way to use generics in verilog?" the use of
parameters is mentioned. I believe that in VHDL it is possible to
override selected generics and leave the remaining as default; i.e. you
don't have to provide values for all generics if you only want to change
one.

Is there a way to do this in Verilog? For example

module Timing( Clock, Reset, Out );
parameter FastClockDiv = 4;
parameter SlowClockDiv = 16;
...

To instantiate with the defaults use

Timing T1( .Clock(A), .Reset(B), .Out(C) );

To instantiate overriding both parameters use

Timing #(5, 24) T1( .Clock(A), .Reset(B), .Out(C) );

How do I instantiate just overriding the FastClockDiv and leave
SlowClockDiv as the default from the module?

Thanks,
Ben
Click to expand...
 
Ben Heard <BenH@cipheroptics.com> wrote in message news:<3f588fed@btitelecom.net>...
comp.lang.verilog,

In the thread "Is there a way to use generics in verilog?" the use of
parameters is mentioned. I believe that in VHDL it is possible to
override selected generics and leave the remaining as default; i.e. you
don't have to provide values for all generics if you only want to change
one.

Is there a way to do this in Verilog? For example

module Timing( Clock, Reset, Out );
parameter FastClockDiv = 4;
parameter SlowClockDiv = 16;
...

To instantiate with the defaults use

Timing T1( .Clock(A), .Reset(B), .Out(C) );

To instantiate overriding both parameters use

Timing #(5, 24) T1( .Clock(A), .Reset(B), .Out(C) );

How do I instantiate just overriding the FastClockDiv and leave
SlowClockDiv as the default from the module?

Thanks,
Ben
Click to expand...



Ben,

You do not have to specify all parameters. You can only
specify the first parameter:

Timing #(5) T1( .Clock(A), .Reset(B), .Out(C) );

Or you can also selectively modify any other parameters
as well, by using "defparam":

defparam top.T1.SlowClockDiv = 123;

and instantiate the module without implicit parameter
passing:

Timing T1( .Clock(A), .Reset(B), .Out(C) );

Regards,
rudi
========================================================
ASICS.ws ::: Solutions for your ASIC/FPGA needs :::
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It seems that it is possible to set defaults only for parameters at
the end of parameter declaration list.
For example, your example will work fine taking default value for the
second parameter SlowClockDiv if you don't specify it within parameter
quotes:

Timing #(5) T1( .Clock(A), .Reset(B), .Out(C) );

However, it's impossible to set default for the first parameter while
redefining the second one.

Regards,
Alexander Gnusin
www.TCLforEDA.net


Ben Heard <BenH@cipheroptics.com> wrote in message news:<3f588fed@btitelecom.net>...
comp.lang.verilog,

In the thread "Is there a way to use generics in verilog?" the use of
parameters is mentioned. I believe that in VHDL it is possible to
override selected generics and leave the remaining as default; i.e. you
don't have to provide values for all generics if you only want to change
one.

Is there a way to do this in Verilog? For example

module Timing( Clock, Reset, Out );
parameter FastClockDiv = 4;
parameter SlowClockDiv = 16;
...

To instantiate with the defaults use

Timing T1( .Clock(A), .Reset(B), .Out(C) );

To instantiate overriding both parameters use

Timing #(5, 24) T1( .Clock(A), .Reset(B), .Out(C) );

How do I instantiate just overriding the FastClockDiv and leave
SlowClockDiv as the default from the module?

Thanks,
Ben
Click to expand...
 
chtruk@yahoo.com (Marcin) wrote in message news:<cf56decc.0309051056.42b4590b@posting.google.com>...
If you want to map only the second parameter you can use mapping by
name :
Timing #(.SlowClockDiv(24)) T1( .Clock(A), .Reset(B), .Out(C)
If your compilator doesn't support this construct (it's quite new
feature - introduced in verilog 2001 if I'm not wrong).
Click to expand...
You are correct, this was introduced in Verilog-2001. I think that
all of the leading tools support this particular extension now.
 
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