More about metastability

[Luiz Carlos]

Metastability occurs when we don't respect setup and/or hold times.
But what does happen when the input for the flip-flop is a DC signal
between Vil and Vih? (Or it changes so slowly that looks like a
constant.)

My guess is there is a voltage, let's say Vth, that:
If Vin < Vth => DOUT = 0 after a delay
If Vin > Vth => DOUT = 1 after a delay
The delay grows as Vin approximates to Vth.

Am I right?

Luiz Carlos

 

[Alvin Andries]

"Luiz Carlos" <oen_br@yahoo.com.br> wrote in message
news:8471ba54.0309040255.3d79ed94@posting.google.com...

Metastability occurs when we don't respect setup and/or hold times.
But what does happen when the input for the flip-flop is a DC signal
between Vil and Vih? (Or it changes so slowly that looks like a
constant.)

My guess is there is a voltage, let's say Vth, that:
If Vin < Vth => DOUT = 0 after a delay
If Vin > Vth => DOUT = 1 after a delay
The delay grows as Vin approximates to Vth.

Am I right?

Luiz Carlos

Hi Luiz,

You're right.

Things could even be worse: in cmos technology, applying a voltage around Vt
at an input consisting of 2 complementary transistors will cause both fets
to conduct, resulting in local excessive power dissipation. Depending on the
exact design of the input, this may even lead to permanent damage. Assuming
that you're using a modern fpga, this is most likely solved by the
manufacturer by using an input with hysteresis. As a counter example: I've
seen diagrams where a 4000 (or 74HC00) is used as voltage controlled sine
oscillator.

Regards,
Alvin.

 

[Austin Lesea]

Alvin,

One common mis-conception is that you can "hurt" or damage the FPGA by having
the input voltage float at exactly the wrong point.

Un-true: the IOBs are designed with sufficient metal and device contacts to
remain in contention forever without damage. The ~500 uA of contention is
hardly noticeable in the overall scheme of things.

So, don't let inputs float (bad practice) but don't stress about it, as no
damage will result in our FPGA input structures.

If you think about it, how can we offer LVDS, HSTL, SSTL, GTL, LVCMOS all on the
same pin without taking this into account?

Austin

Alvin Andries wrote:

"Luiz Carlos" <oen_br@yahoo.com.br> wrote in message
news:8471ba54.0309040255.3d79ed94@posting.google.com...
Metastability occurs when we don't respect setup and/or hold times.
But what does happen when the input for the flip-flop is a DC signal
between Vil and Vih? (Or it changes so slowly that looks like a
constant.)

My guess is there is a voltage, let's say Vth, that:
If Vin < Vth => DOUT = 0 after a delay
If Vin > Vth => DOUT = 1 after a delay
The delay grows as Vin approximates to Vth.

Am I right?

Luiz Carlos

Hi Luiz,

You're right.

Things could even be worse: in cmos technology, applying a voltage around Vt
at an input consisting of 2 complementary transistors will cause both fets
to conduct, resulting in local excessive power dissipation. Depending on the
exact design of the input, this may even lead to permanent damage. Assuming
that you're using a modern fpga, this is most likely solved by the
manufacturer by using an input with hysteresis. As a counter example: I've
seen diagrams where a 4000 (or 74HC00) is used as voltage controlled sine
oscillator.

Regards,
Alvin.

 

[Luiz Carlos]

Hi Austin,

Does Xilinx apply hysteresis (as Alvin said) on CLPLD/FPGA inputs
(when they are configured as LVTTL, CMOS,... etc, i.e., they don't use
that input comparators)?

Sorry about the parentheses, I'm trying hard to keep them at just one
level!

Luiz Carlos.

 

[Austin Lesea]

Luiz,

All I know is that Virtex II and II Pro both have hysteresis on the
LVCMOS/LVTTL single ended input buffer. It is always there, and can not
be turned off. It is about 100 mV.

I know that in some of our CPLDs you have an attribute you can turn on and
off for hysteresis.....

The comparators in VII, VII Pro do not have hysteresis (SSTL. HSTL, LVDS).

Don't remember the answers for Virtex, Virtex E, Spartan II or Spartan
IIE, a search of the answers database might turn them up

Austin

Luiz Carlos wrote:

Hi Austin,

Does Xilinx apply hysteresis (as Alvin said) on CLPLD/FPGA inputs
(when they are configured as LVTTL, CMOS,... etc, i.e., they don't use
that input comparators)?

Sorry about the parentheses, I'm trying hard to keep them at just one
level!

Luiz Carlos.