Monte carlo simulation types - last questions

[spectrallypure]

Hello all! I am trying to understand the differences between the two
major types of montecarlo analysis that can be run in Cadence (process-
only and mismatch-only) , but I am having trouble trying to interpret
their definitions with respect to the actual results they predict.

I am simulating a very simple dynamic circuit, consisting of a
differential pair whose output currents are used to charge identical
capacitors. The variable of interest is the differential voltage
accross the capacitors after a certain integration time. I am running
monte carlo simulations CONSIDERING ONLY the statistical variations in
MOS transistors (not in the capacitors). I have run both types of
monte carlo simulations twice: first with nominal gate sizes and then
a second time doubling both gate dimensions in order to quadruplicate
the area. The results are as follows; the measured quantity is the
deviation (spread) from the nominal differential output voltage that
is expected:

Version 1) Diff. pair with dimensions L1, W1 (A1=W1.L1):
-Mismatch-only simulation: Spread(Vout,diff) = 20mV approx.
-Process-only simulation: Spread(Vout,diff) = 100mV approx.

Version 2) Diff. pair with dimensions L2=2L1, W2=2W1(A2=4A1):
-Mismatch-only simulation: Spread(Vout,diff) = 10mV approx.
-Process-only simulation: Spread(Vout,diff) = 100mV approx.

As expected, the spread in the differential output voltage is halved
by a four-fold in the gate area. However, in both cases the "process"
variations overwhelm the "mismatch" variations. What's worse, these
process variations don't seem to improve at all by increasing the
transistor areas!!! :O

The questions are, then,

-If I were to manufacture both versions of this circuit tomorrow,
what would be the (worst-case) expected spreads in the output voltage
that I would get? 10 and 20mV, respectively? 100mV in both cases?
neither?

-How in the world can I reduce the "process variations" through
design? Are these variations something that the designer can combat-
with, or rather live-with?

Sorry if this all is a little off-topic; I really look forward to hear
what is the generalized undestanding about the practical results of
monte carlo analysis, and what the experienced folks would do in this
situation.

Thanks in advance for any ideas!

Cheers,

Jorge.

 

[S. Badel]

spectrallypure wrote:

Hello all! I am trying to understand the differences between the two
major types of montecarlo analysis that can be run in Cadence (process-
only and mismatch-only) , but I am having trouble trying to interpret
their definitions with respect to the actual results they predict.

Hello Jorge,

It's very simple, actually. Variations are usually modeled with two components : "Process" or
"Systematic", and "random" or "mismatch". Process variations affect all components in the same way,
while mismatch affects each component individually. In effect, process variation describe the
variation of the mean value, and mismatch describe the individual variations around the mean.

When circuits are fabricated, the resulting parameter values can vary quite a lot ; however, they
are reasonably stable within the same die. Say you have two samples of a chip, and you measure the
threshold voltage of the N-channel transistors. It would not be surprising to see a difference of
100 or 200 mV between transistors of sample #1 and of sample #2, but if you compare the transistors
from sample #1 only, their values will match much better - say, +/- 10mV (I'm making up the values...).

Process variations can usually be cancelled by proper design (biasing, use of differential
circuits), while for mismatch it's much harder.

In your example, the current difference depends on the gm of transistors, hence the result is
affected by process variations. You could get rid of this dependency, though, by adjusting the bias
current to have a constant gm, independent of process variations. Think of a current mirror as a
very simple example of such process-independant design - the drain current of the source transistor
is proportional to mu * cox * w/l * (vgs - vt)^2, and its gate voltage is generated by a
diode-connected mosfet giving vg = vt + sqrt(Iref / (mu * cox * w/l)) resulting in a drain current
Id = Iref independant of process variations (but sensitive to mismatch, since it relies on both
transistors being identical).

Your circuit is sensitive to mismatch also - of course - since it relies on the fact that both
transistors are identical. This dependency can be reduced by increasing the transistor sizes, as you
have seen.


Hope this clears up some doubts,
Stéphane

 

[Riad KACED]

Hi Jorge,

1. I won't add any comment on top of Stéphane's since I had roughly
the same idea. I put together few slides about this topic a little
while back. You might be interested sparing couple of minutes of your
time reading through them. You are lucky, they are in English ...
http://groups.google.com/group/riad-kaced-usenet-group/web/MC-simus.ppt

2. They are indeed few techniques to overcome the process/matching
inaccuracies. As Stéphane mentioned earlier, increasing the sizes of
transistors will improve the matching. You can't keep increasing the
sizes though since you will trade with your design's area. Other
techniques like common centroid layouts ... etc would apply to enhance
things. I guess you Analog books are all taking about this.

One of the common things in use nowadays is digital calibration and I
have used these techniques myself in my youngest days when I was doing
some proper design work. The idea is to trim your matched design with
some logic around. The whole idea is to spend less effort in making a
perfect analog design and then recover the mismatches with some
logics. This works very well as lots of Analog designs are moving
towards pure CMOS modern technology nodes where the logic is very
cheap.

If you are lucky enough to work in a BiCMOS process, then try to use
the bipolars as much as possible for the matching pairs. The Bips are
far better than the MOS in terms of matchings. They have got all the
well known disadvantages over the MOS as well ;-)

Cheers,
Riad.

 

[spectrallypure]

Stéphane, Riad, I cannot thank you enough for your (continuous) help.
Based on your explanations and after performing some basic simulations
of mirrors and differentials in Cadence, I think I finally understand
clearly what are these two types of simulations all about. And only
now the montecarlo results of my project begin to make sense!

Thanks again for your help -You don't really have an idea of the
difference your advise can make, specially when one has no one sitting
next to ask this kind of questions. Thanks and thanks again.

Cheers,

Jorge.