Mono from 1/2 x 4013

[Terry Pinnell]

Anyone know how to make a mono from half a 4013 please?

I've spent a while trying, but so far failed. I was pretty sure
I'd done it a year or two ago, but darned if I can find anything, so
maybe it was wishful thinking.

--
Terry Pinnell
Hobbyist, West Sussex, UK

 

[Rolavine]

From: Terry Pinnell

Anyone know how to make a mono from half a 4013 please?

Well one way (I think) is to put D to VDD. clock the flop (mono) on a positive
trans of the clk, feed the q output through a resistor to Res, and put reset
through a cap to ground. You will also need a high value bleed resistor from
res to ground.

Rocky

 

[John Fields]

On Sun, 03 Oct 2004 16:54:48 +0100, Terry Pinnell
<terrypinDELETE@THESEdial.pipex.com> wrote:

Anyone know how to make a mono from half a 4013 please?

---

+------------+
| |
| +-[<CR]-+ |
+--+--+ | |
Vcc>--------|D R Q|-+--[R]--+
START>------|> | |
| S | [C]
+--+--+ |
| |
GND>-----------+------------+

--
John Fields

 

[Ken Smith]

In article <k380m09arsectd1qvduu6dok331neeupfl@4ax.com>,
Terry Pinnell <terrypinDELETE@THESEdial.pipex.com> wrote:

Anyone know how to make a mono from half a 4013 please?

I've spent a while trying, but so far failed. I was pretty sure
I'd done it a year or two ago, but darned if I can find anything, so
maybe it was wishful thinking.

You feed the Q back to the R through an RC delay.

--
--
kensmith@rahul.net forging knowledge

 

[Rich Grise]

On Sunday 03 October 2004 03:21 pm, Terry Pinnell did deign to grace us with
the following:

Thanks for all those. I'll try them tomorrow. Pleased to see I wasn't
imagining it.

Not half as pleased as I am to see it's possible! ;-D ;-D ;-D

Cheers!
Rich

 

[Tony Williams]

In article <cjr8cc02msi@drn.newsguy.com>,
Winfield Hill <Winfield_member@newsguy.com> wrote:

This is a good data point. When the CMOS system is shutoff it's
powered for a short while through the gate until the capacitor
is discharged. The cases I'm familiar with have all used much
smaller capacitors values, for short logic time delays, and have
been battery applications that had low supply drains so the gate-
powered condition was an innocuous one.

I think everything conspired the other way in the case
of that customer. High value caps, a topology that kept
them charged to (a high) Vcc for most of the time, and
a Vcc that went down quickly.

--
Tony Williams.

 

[Jim Thompson]

On Tue, 05 Oct 2004 16:32:01 +0100, Terry Pinnell
<terrypinDELETE@THESEdial.pipex.com> wrote:

Terry Pinnell <terrypinDELETE@THESEdial.pipex.com> wrote:

John Fields <jfields@austininstruments.com> wrote:

On Sun, 03 Oct 2004 21:01:06 GMT, Fred Bloggs <nospam@nospam.com
wrote:


Correction- R,S inactive low for 4000:
View in a fixed-width font such as Courier.


V+
|
+-------+
| |
| +----+-----+ T= k xRTxCT
| | VDD | +----------+
+--|D Q |-------+---> | |
| | | | |
| , | \ | |
+--- | 4013 | RT ---+ +--
| | | \
| | | /
| >------|\ | |
| |/ | CT |
---+ | _ | | | |
| Q |--| |--+
| | | | |
| | |
| S R | |
+----------+ |
| | |
| +--/\/\----+
|
---
'0'

---
Clever!

Thanks for all those. I'll try them tomorrow. Pleased to see I wasn't
imagining it.

Here's my successful result with the 'standard' circuit. I've only
simulated, not breadboarded it, so do you reckon that 'spike' in the
diode variation is real or an artifact of my simulation?

http://www.terrypin.dial.pipex.com/Misc/4013mono1.gif

Fred: I also tried your version, but the simulation failed with error
"Float invalid operation exception". What's the suggested value of the
lower R please? (I arbitrarily tried 1k, 10k and 100k, with same error
message.)

Improper simulation/use. What about the ESD structure on "R" ??

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[John Fields]

Here's my successful result with the 'standard' circuit. I've only
simulated, not breadboarded it, so do you reckon that 'spike' in the
diode variation is real or an artifact of my simulation?

http://www.terrypin.dial.pipex.com/Misc/4013mono1.gif

---
I just wired it up and... no spike.

Also, with a 0.47ľF Mylar and 470k in there I get about 270ms.

Interesting way to measure Vth of the RESET...

--
John Fields

 

[Winfield Hill]

Fred Bloggs wrote...

With your timing, a 1M resistor in series with RESET is more than
adequate. Win Hill's claim of that race/noise-prone minimalist circuit
is overstated. It is NOT a 'standard' circuit and my library of
historical logic design goes back further than his. He is basing his
opinion on some non-critical application in a cheap mass-produced gizmo
he reverse engineered. I advise against using that 'thing' of his in any
application that can be disrupted by "runt pulse" behavior. The circuit
is just plain anti-digital, and a little wisp of a few uA of clamp diode
current for any MSI IC is a non-event.

I don't have time now to refute Fred's mis-characterizations and
incorrect facts and arguments point by point, so I'll be forced
to just say WRONG and leave it at that. Anyone who's interested
can observe the juxtaposed claims and investigate for themselves.


--
Thanks,
- Win

(email: use hill_at_rowland-dotties-org for now)

 

[Terry Pinnell]

John Fields <jfields@austininstruments.com> wrote:

Here's my successful result with the 'standard' circuit. I've only
simulated, not breadboarded it, so do you reckon that 'spike' in the
diode variation is real or an artifact of my simulation?

http://www.terrypin.dial.pipex.com/Misc/4013mono1.gif

---
I just wired it up and... no spike.

I repeated the simulation with various diodes types. As luck would
have it, the type I chose for my earlier test (the 1N4148, which I use
as default for Si small signal types out of habit), gave by far the
largest spike. Some gave no measurable spike at all. Here's the
summary of my arbitrary selection:

Type Spike amplitude
------- ---------------
1N4148 1.40
1N914 0.75
1N4001 0.00
1N458 0.17
1N3070 0.08
1N34 (Ge) 0.00

BTW, what type did you use?

--
Terry Pinnell
Hobbyist, West Sussex, UK

 

[Winfield Hill]

Terry Pinnell wrote...

I repeated the simulation with various diodes types. As luck would
have it, the type I chose for my earlier test (the 1N4148, which
I use as default for Si small signal types out of habit), gave by
far the largest spike. Some gave no measurable spike at all.

Put a 3.3k resistor in series with the diode.


--
Thanks,
- Win

(email: use hill_at_rowland-dotties-org for now)

 

[John Fields]

On Thu, 07 Oct 2004 09:46:49 +0100, Terry Pinnell
<terrypinDELETE@THESEdial.pipex.com> wrote:

BTW, what type did you use?

1N4148, and for the rest of it: 470K, 0.47ľF Mylar, Motorola
MC14013BCB.

BTW, the period was 170ms, not the 270ms I posted earlier, and I used
an HP54602B to view the waveform.

--
John Fields

 

[Terry Pinnell]

Winfield Hill <Winfield_member@newsguy.com> wrote:

Terry Pinnell wrote...

I repeated the simulation with various diodes types. As luck would
have it, the type I chose for my earlier test (the 1N4148, which
I use as default for Si small signal types out of habit), gave by
far the largest spike. Some gave no measurable spike at all.

Put a 3.3k resistor in series with the diode.

Thanks. I thought at first that you must be saying there was a real
spike, and that this would remove it. But then I realised you meant
only the simulation.

Indeed - just tried it with the resistor, and it removes it. Can you
clarify what's happening here please?

--
Terry Pinnell
Hobbyist, West Sussex, UK

 

[John Fields]

On Sat, 09 Oct 2004 13:49:42 +0100, Terry Pinnell
<terrypinDELETE@THESEdial.pipex.com> wrote:

John Fields <jfields@austininstruments.com> wrote:


Here's my successful result with the 'standard' circuit. I've only
simulated, not breadboarded it, so do you reckon that 'spike' in the
diode variation is real or an artifact of my simulation?

http://www.terrypin.dial.pipex.com/Misc/4013mono1.gif

---
I just wired it up and... no spike.

Also, with a 0.47ľF Mylar and 470k in there I get about 270ms.

I got around to breadboarding it today. Agreed, no spike. But did you
notice the small 'excursion', with or without the diode? With Vcc of
9V it's about 700 mV high and lasts about 300 us. 5V supply gave about
330 mV.

http://www.terrypin.dial.pipex.com/Images/4013MonoDiodeSpike.gif

---
Looks like an undercompensated scope probe.
---

I used 0.47ľF Mylar and 1M with a couple of types, HCF4013BE and
CD4013BCN, giving about 250 mS.

BTW, do you follow Win's suggestion to add a 3k3 resistor in series
with the diode?
news:ck376e02r8p@drn.newsguy.com

---
No.
---

Can you remind me what advantage is offered by the diode please?

---
Sure. Without it the period of the one-shot would vary with the charge
left in the cap, which would depend upon the time between when the
one-shot timed out and when it was triggered again. That is, the
diode steers current around the resistor when Q goes low, discharging
the cap quickly.

--
John Fields

 

[Terry Pinnell]

John Fields <jfields@austininstruments.com> wrote:

On Sat, 09 Oct 2004 13:49:42 +0100, Terry Pinnell
terrypinDELETE@THESEdial.pipex.com> wrote:

John Fields <jfields@austininstruments.com> wrote:


Here's my successful result with the 'standard' circuit. I've only
simulated, not breadboarded it, so do you reckon that 'spike' in the
diode variation is real or an artifact of my simulation?

http://www.terrypin.dial.pipex.com/Misc/4013mono1.gif

---
I just wired it up and... no spike.

Also, with a 0.47ľF Mylar and 470k in there I get about 270ms.

I got around to breadboarding it today. Agreed, no spike. But did you
notice the small 'excursion', with or without the diode? With Vcc of
9V it's about 700 mV high and lasts about 300 us. 5V supply gave about
330 mV.

http://www.terrypin.dial.pipex.com/Images/4013MonoDiodeSpike.gif

---
Looks like an undercompensated scope probe.
---

Ah, so it does, thanks - another puzzle solved.

I used 0.47ľF Mylar and 1M with a couple of types, HCF4013BE and
CD4013BCN, giving about 250 mS.

BTW, do you follow Win's suggestion to add a 3k3 resistor in series
with the diode?
news:ck376e02r8p@drn.newsguy.com

---
No.
---

As you've probably seen, Win's now given a detailed explanation.

Can you remind me what advantage is offered by the diode please?

---
Sure. Without it the period of the one-shot would vary with the charge
left in the cap, which would depend upon the time between when the
one-shot timed out and when it was triggered again. That is, the
diode steers current around the resistor when Q goes low, discharging
the cap quickly.

Understood, thank you.

--
Terry Pinnell
Hobbyist, West Sussex, UK

 

[Terry Pinnell]

Winfield Hill <Winfield_member@newsguy.com> wrote:

Terry Pinnell wrote...

Can you clarify what's happening here please?

Winfield Hill <Winfield_member@newsguy.com> wrote:

. ____
. + --|D Q|---+---+--- timed pulse OUT
. IN ----|> | | _|_ t = 0.7 RC
. __ |__R_| R /_\
. __/ |_____|___| diode that needs
. | a series resistor
. edge- C
. trigger |
. gnd

I have no idea why your simulation shows a spike, but in real life
the capacitor-discharge diode without a series resistor creates a
supply short on the Q pin at the oneshot-timeout flip-flop reset.
More accurately, it forces a full supply-voltage signal across
the logic-low-level Q output, causing a high current through the
ground pin of the CMOS logic IC until the capacitor is discharged.
A resistor added in series with the diode limits this current, and
only modestly decreases the maximum duty ratio the timer can handle.

BTW, in the drawing above I show the oneshot time** as t = 0.7 RC,
but actually this time ranges from 0.35 to 1.2 RC, because the CMOS
gate threshold Vt ranges from 30 to 70% of the supply voltage Vs.
Of course the RC value tolerances must also be considered. The very
poor accuracy of this circuit is one reason it's usually used only
for short non-critical time delays in a logic circuit (if the value
of C is much over 500pF, then a series resistor should be added to
the flip-flop's R terminal, as discussed elsewhere in this thread).

In contrast to the 4013 timer inaccuracy of +70% to -50%, the common
MC14538 oneshot inaccuracy spec is nearly 10x better, +6% to -8.6%
(at 10V). Clearly this is a much better CMOS part to use for timers.

** The timing formula is t = k R C, where k = ln (1 / (1 - Vt/Vs)).
If the threshold voltage is exactly 1/2 of the supply, then k is the
natural log of 2, or k = 0.69315 or 0.693, which is a number many of
us have memorized.

Many thanks, Win.

--
Terry Pinnell
Hobbyist, West Sussex, UK

 

[Fred Bloggs]

Terry Pinnell wrote:

Fred: I'd closed up the workshop before I realised I'd forgotten to
try your version; next time!

There is nothing to "try"- I have been using the circuit for a long
time. There is no problem with a few uA of clamp diode current of any
duration. But then re-trigger recovery time has never been an issue-
although it is easily adapted to this circuit too.

 

[Winfield Hill]

Terry Pinnell wrote...

Winfield Hill wrote:

Terry Pinnell wrote...

I repeated the simulation with various diodes types. As luck would
have it, the type I chose for my earlier test (the 1N4148, which
I use as default for Si small signal types out of habit), gave by
far the largest spike. Some gave no measurable spike at all.

Put a 3.3k resistor in series with the diode.

Thanks. I thought at first that you must be saying there was a real
spike, and that this would remove it. But then I realised you meant
only the simulation.

Indeed - just tried it with the resistor, and it removes it. Can you
clarify what's happening here please?

.. ____
.. + --|D Q|---+---+--- timed pulse OUT
.. IN ----|> | | _|_ t = 0.7 RC
.. __ |__R_| R /_\
.. __/ |_____|___| diode that needs
.. | a series resistor
.. edge- C
.. trigger |
.. gnd

I have no idea why your simulation shows a spike, but in real life
the capacitor-discharge diode without a series resistor creates a
supply short on the Q pin at the oneshot-timeout flip-flop reset.
More accurately, it forces a full supply-voltage signal across
the logic-low-level Q output, causing a high current through the
ground pin of the CMOS logic IC until the capacitor is discharged.
A resistor added in series with the diode limits this current, and
only modestly decreases the maximum duty ratio the timer can handle.

BTW, in the drawing above I show the oneshot time** as t = 0.7 RC,
but actually this time ranges from 0.35 to 1.2 RC, because the CMOS
gate threshold Vt ranges from 30 to 70% of the supply voltage Vs.
Of course the RC value tolerances must also be considered. The very
poor accuracy of this circuit is one reason it's usually used only
for short non-critical time delays in a logic circuit (if the value
of C is much over 500pF, then a series resistor should be added to
the flip-flop's R terminal, as discussed elsewhere in this thread).

In contrast to the 4013 timer inaccuracy of +70% to -50%, the common
MC14538 oneshot inaccuracy spec is nearly 10x better, +6% to -8.6%
(at 10V). Clearly this is a much better CMOS part to use for timers.

** The timing formula is t = k R C, where k = ln (1 / (1 - Vt/Vs)).
If the threshold voltage is exactly 1/2 of the supply, then k is the
natural log of 2, or k = 0.69315 or 0.693, which is a number many of
us have memorized.


--
Thanks,
- Win

(email: use hill_at_rowland-dotties-org for now)