P
priya
Guest
hi all
i m using integer data type in VHDL .i have to perform modulo
operation.
but the problem i m facing is that the operand must be a constant
like
A<= (A+1) MOD X
where X is not a constant.
during synthesis i m facing this problem
plz help out soon
one more thing
in case of for loop
for i in 0 to N loop
end loop
again N is sppsed to be fixed
best regards
priya
i m using integer data type in VHDL .i have to perform modulo
operation.
but the problem i m facing is that the operand must be a constant
like
A<= (A+1) MOD X
where X is not a constant.
during synthesis i m facing this problem
plz help out soon
one more thing
in case of for loop
for i in 0 to N loop
end loop
again N is sppsed to be fixed
best regards
priya