Q
qharz
Guest
Hi
I am quite fresh with vhdl and i have a problem. How to realize modulo
function using signals not variables?
For example: modulo_signal <= sample_signal mod 65536;
Best regards,
qharz
I am quite fresh with vhdl and i have a problem. How to realize modulo
function using signals not variables?
For example: modulo_signal <= sample_signal mod 65536;
Best regards,
qharz