modules???

[A.Q]

Hi guys,,
We use 'component' in VHDL instead of 'entity' to ensure
seperate blocks,, Is there a command in Verilog i can use instead of
'module' so that the different modules do not merge while
synthesizing???? Plz reply.

 

[Jonathan Bromley]

On Sun, 30 Aug 2009 12:59:24 -0700 (PDT), "A.Q" wrote:

We use 'component' in VHDL instead of 'entity' to ensure
seperate blocks,

Really? I don't believe it makes any difference
once the entire design is elaborated. Components
allow you to describe a VHDL architecture that
contains black-box instances, but at some point the
synthesis tool must fill in the black boxes and
then the component boundaries may be merged if
synthesis thinks it's a good idea.

Is there a command in Verilog i can use instead of
'module' so that the different modules do not merge while
synthesizing????

No. Apply a "don't touch" attribute for synthesis,
or enable the "preserve hierarchy" feature of your
synthesis tool. Same applies in VHDL too. Hierarchy
flattening by synthesis is a tool flow issue, not a
VHDL or Verilog language issue.
--
Jonathan Bromley, Consultant

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[Andy]

What Jonathan said...

And I might add that once you eliminate vhdl components, and directly
instantiate entities instead, your life will get much easier for the
vast majority of use cases.

Configurations are extremely powerful when needed, but they're just
not needed that often, so carrying around the baggage of component and
configuration declarations is just not worth it in most cases. I've
seen a few really powerful uses of configurations in test benches, but
none in RTL for synthesis.

If you need the flexibility that configurations provide, that can be
accomplished with generate statements and entity instantiations.

Andy