modules

[pat]

i have 2 modules.
one i call 'main'
one is called 'counter' which is instantiated in main.

main has...
clk input
counter_input
[7:0] output

counter has...
clk input
counter output

(i am using xilinx web pack verilog design (not schematic design)

i instantiate counter in main sending it clk only. inside counter i
have always @(posedge clk) counter <= counter + 1;

in main, i...
also have the same clk.
what i am looking to do is have the output of counter go into the input
of main.

i tried wire, assign and a bunch of other stuff.

this is what i am thinking
1. counter and main are in sink cause they use the same clk.
2. is my counter value lost when i go out of instantiated counter?
3. if need be i can cut/paste my two modules

thanks

 

[pablo aimar]

Hi
wire should work.

-rao

 

[Chris Alexander]

Posting your modules would make it easier to debug. It sounds like
you are trying to wire something _inside_ of main to an _input_ of
main, which is not legal.

I would guess you need something like these below. The outputs of the
counter are connected to a "wire" that is also the main module output:

module main;
input clk;
output [7:0] count;

wire [7:0] count;

counter counter_instance (.clk(clk), .count(count));

endmodule

module counter;
input clk;
output [7:0] count;

reg [7:0] count;

always @(posedge clk)
count <= count + 1;

endmodule

raonpc@gmail.com (pablo aimar) wrote in message news:<95ef6f72.0409101627.45e408bf@posting.google.com>...

Hi
wire should work.

-rao