module ports vs parameters

[johnp]

I like to declare my modules like
module foo (
input a,
input b,
output c
);

and not use the older
module foo (a, b, c);
input a;
input b;
output c;

Now, one advantage of the older style is that you can sneak an include
statement in
that defines port widths via parameters within the include file:
module foo (a, b, c);
`include "my_params.vh"
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
output c;


Is there a way to to use the new declaration format, but style have an
`include file
that will have parameters that define signal widths? I realize that
if i use `define
statements, I can put the include file before the module declaration,
but I'd
prefer to stick with parameters.

Also - I know about the format
module foo #(
parameter WIDTH = 1
) (
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
output c
);
But this doesn't let me use the include file.


Any suggestions?

Thanks!

John Providenza

 

[Jonathan Bromley]

On Mon, 6 Jul 2009 13:23:09 -0700 (PDT), johnp wrote:

Also - I know about the format
module foo #(
parameter WIDTH = 1
) (
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
output c
);
But this doesn't let me use the include file.

Why not? You'll need to change it just a little
(comma separators, no terminating semicolon) but
this should be OK:

module foo #{
`include "params.vh"
) (
input [WIDTH-1:0] a,
...

params.vh now contains code like this...

parameter WIDTH = 1

or

parameter WIDTH = 1,
STUFF = 10

or

parameter WIDTH = 1,
parameter STUFF = 10

There is nothing in the rules to say that an
include file must be a syntactically complete unit.
It's just textually included at the appropriate point
in the code. Also, a module with an empty parameter
list in its declaration

module foo #( ) (...);

is OK, so there's no problem if the include file
contains only whitespace.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jonathan Bromley]

On Mon, 06 Jul 2009 21:33:59 +0100, Jonathan Bromley wrote:

params.vh now contains code like this...

parameter WIDTH = 1

or

parameter WIDTH = 1,
STUFF = 10

or

parameter WIDTH = 1,
parameter STUFF = 10

Afterthought: You may want to use the same parameter
file in a testbench or elsewhere. In that case, you can:
if you use the second form I gave...

parameter WIDTH = 1,
STUFF = 10

then it's legal to put it into another module too:

module TB;
`include "params.vh"
; // semicolon must go on a separate line :-(
reg [WIDTH-1:0] a;

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.