Modulator / Demodulator

[john]

Hello,


I need to build the digital frequency modulator and demodulator in
VHDL. I am using Spartan Chip. I have got 48 bits of data. The FPGA is
serial outing each bit at the rising edge of the 1.5MHz clock. I need
to send this data stream, Clock and Synch signal ( which goes high for
the time when FPGA is serial outing the data else stays low)
wirelessly to a receiver. The reciever or demodulator will send the
data, clock and synch signals to a DAC.

Can somebody give me some suggestions that How to proceed with this
project?

Thanks
John

 

[Jonathan Bromley]

On Fri, 16 May 2008 08:16:31 -0700 (PDT), john wrote:

I need to build the digital frequency modulator and demodulator in
VHDL. I am using Spartan Chip. I have got 48 bits of data. The FPGA is
serial outing each bit at the rising edge of the 1.5MHz clock. I need
to send this data stream, Clock and Synch signal ( which goes high for
the time when FPGA is serial outing the data else stays low)
wirelessly to a receiver. The reciever or demodulator will send the
data, clock and synch signals to a DAC.

Can somebody give me some suggestions that How to proceed with this
project?

I suspect you'll get more response if you make the specification
clearer. If you need wireless comms, you need some kind of "air
interface" - for example, are you planning to use 433MHz ISM?
Or perhaps the radio-control channels commonly used for toys?
You could consider frequency, amplitude or phase modulation;
do you have a choice, or is that already determined for you?
Most of all, what output are you expecting from your FPGA?
Do you intend to generate the RF signal directly from the
FPGA itself, or do you intend a lower-frequency signal that
will then be modulated on to the RF by other equipment?

To recover the clock signal at the receiver, you'll need to
use some coding scheme that provides an appropriate stream
of transitions that the receiver can lock on to. To recover
the "synch" (enable) signal, you'll need some way to make the
communication link indicate when it's idle, using some special
coding pattern that's guaranteed not to appear in the real
data stream.

These are all problems that have been solved many times before,
of course; any good book on digital communications techniques
should give you a host of ideas.
--
Jonathan Bromley, Consultant

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