modular addition of std_logic_vector

[Eli Bendersky]

Hello all,

I calculate the checksum of several bytes roughly as follows:

signal aa, bb, cc, dd: std_logic_vector(7 downto 0);

....
....
aa <= x"F1";
bb <= x"45";
cc <= x"17";
....
....
dd <= aa + bb + cc;

Now, the answer I expect to get from this in dd is x"4D", since it's
the result of the addition modulo 256. And indeed I receive this answer
in simulation.

What I want to ask is what guarantees me that this is the answer this
VHDL should give, in simulation and in synthesis. Is this guaranteed by
the VHDL standard ? By one of the libraries - like numeric_std ? Which
library then ?

Thanks in advance