Guest
Hello all,
I need to do a massive surgery on an existing RTL code.
The objective is to generate a "hard" hierarchical layer around a VHDL
Function, by "hard" I mean that it'll be kept after synthesis - this
will help me in tools in the Flow downstream synthesis.
I thought about converting the function to a component first and then
connecting it to the processes in which the original function was
called in. This looks like "easier said than done..."
As an alternative I would like to be able to isolate a small fraction
of this specific, called, function, e.g. a multiplication , and have
solid hierarchical boundary of this operation only.
I assume a Synthesis that is non aggressive, i.e: does not ungroup in
any way and does not do any boundary optimization.
Any idea on how to do this will be truly appreciated.
thx
\ZeevY
I need to do a massive surgery on an existing RTL code.
The objective is to generate a "hard" hierarchical layer around a VHDL
Function, by "hard" I mean that it'll be kept after synthesis - this
will help me in tools in the Flow downstream synthesis.
I thought about converting the function to a component first and then
connecting it to the processes in which the original function was
called in. This looks like "easier said than done..."
As an alternative I would like to be able to isolate a small fraction
of this specific, called, function, e.g. a multiplication , and have
solid hierarchical boundary of this operation only.
I assume a Synthesis that is non aggressive, i.e: does not ungroup in
any way and does not do any boundary optimization.
Any idea on how to do this will be truly appreciated.
thx
\ZeevY