modelsim warnings

[srinukasam]

HI TO ALL
I designed a mux which gives multiple outputs. but at the time of
simulation with model sim iam getting some warning with generate command.
And my testbench is working for my design.the only problem is warning.i
want to get rid of those warnings.pls help me.

Warnings..

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__5/mut1
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an
arithmetic operand, and it has been converted to 0.
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__5/mut1
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__4/mut1
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an
arithmetic operand, and it has been converted to 0.
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__4/mut1
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__3/mut1
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an
arithmetic operand, and it has been converted to 0.
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__3/mut1
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__2/mut1
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an
arithmetic operand, and it has been converted to 0.
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__2/mut1
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__1/mut1
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an
arithmetic operand, and it has been converted to 0.
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__1/mut1
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__0/mut1
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an
arithmetic operand, and it has been converted to 0.
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__0/mut1


DESIGN FOR COMPONENT-----

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mux is
generic ( input_w :integer :=16; --input signal width
ictrl_w :integer :=4); -- individual control signal
width

port(input:in std_logic_vector (input_w-1 downto 0);
ctrl: in std_logic_vector (ictrl_w-1 downto 0);
out_muxut std_logic);
end entity mux;

architecture mux_beh of mux is
begin
out_mux<=input(conv_integer(ctrl));
end architecture mux_beh;

COMPONENT IS USED IN THIS DESIGN -------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY mux_ge IS
generic ( input_w :integer :=16; --input signal width
ictrl_w :integer :=4; -- individual control signal
width
tctrl_w : integer :=24; -- total control signal width--mem
out
no_out,no_ctrl :integer :=6); -- no of output
signals(r),no.of control signals (V)

port( input:in std_logic_vector(input_w-1 downto 0);
tctrl: in std_logic_vector(tctrl_w-1 downto 0);
out_fmuxut std_logic_vector(no_out-1 downto 0));
END ENTITY mux_ge;

--
ARCHITECTURE mux_ge_str OF mux_ge IS

component mux

generic ( input_w :integer :=16; --input signal width
ictrl_w :integer :=4); -- individual control signal
width

port(input:in std_logic_vector(input_w-1 downto 0);
ctrl:in std_logic_vector(ictrl_w-1 downto 0);
out_mux: out std_logic);
end component mux;


BEGIN
ge1:for i in 0 to no_out-1 generate

mut1:mux port map(input,tctrl((i*ictrl_w)+(ictrl_w-1) downto
i*ictrl_w),out_fmux(i));
end generate ge1;


END ARCHITECTURE mux_ge_str;

configuration mux_ge_config of mux_ge is
for mux_ge_str
for all:mux
use entity work.mux(mux_beh);
end for;
end for;
end configuration mux_ge_config;

 

[Hubble]

The error lies in the conv_integer function,
which sees undefined values ("UUU..") at
simulation start. On some simulators,
the warnings can be disabled.

You could create a "wrapper" to conv_integer
and call this:

(not tested)

architecture ...

function my_conv_integer(s: std_logic_vector)
return integer is
begin
if s=(s'range => 'U') then -- avoid warning at start
return 0;
else
return conv_integer(s);
end if;
end my_conv_integer;

begin
....
out_mux<=my_conf_integer(ctrl);
....

 

[Andy Peters]

srinukasam wrote:

hello Hans
i didnt understood what is your replacement for my problem( modelsim
error).
could you please send me some detailed reply.
thank you
bye

Sheesh.

Type the commands that Hans gave you into the ModelSim shell.

-a