ModelSim view internal signals in instantiated verilog modul

M

melinda

Guest
Hi all,

I am simulating a entity with Modelsim (v6.5c). Modelsim
only displays the input/output signals of the simulated top entity.

When I run simulation Modelsim displays only changes of input/outpu
signals of the top entity verilog module i.e. testbench (in objects windo
i.e. in wave window), but nothing happening with signals declared in th
instantiated verilog modules.
(PS: In Cadence SimVision, I know that I was able to see changes of al
signals in testbench and also in instantiated verilog modules, in wav
window)

Is there a way of viewing the internal signals declared in the instantiate
verilog modules in Modelsim in wave window?

Thanks very much

Regards
 
On Nov 3, 2:29 pm, "melinda" <melinda.m...@gmail.com> wrote:
Hi all,

I am simulating a entity with Modelsim (v6.5c). Modelsim
only displays the input/output signals of the simulated top entity.

When I run simulation Modelsim displays only changes of input/output
signals of the top entity verilog module i.e. testbench (in objects window
i.e. in wave window), but nothing happening with signals declared in the
instantiated verilog modules.
(PS: In Cadence SimVision, I know that I was able to see changes of all
signals in testbench and also in instantiated verilog modules, in wave
window)

Is there a way of viewing the internal signals declared in the instantiated
verilog modules in Modelsim in wave window?

Thanks very much

Regards
Click to expand...
Hi Melinda

I assume you're using ModelSim SE?

By default, SE optimizes the design for maximum performance, which
includes removing the capability to log internal nodes.
This optimization is done by the vopt command, which you can call
explicitly after compilation else is run implicitly when you start
vsim (you'll see "** Note: (vsim-3812) Design is being optimized..."
in the transcript).

To enable the ability to log internal signals you must give vopt some
additional parameters
The following will enable access to all objects in the whole design

Explicit vopt:
vopt my_top +acc -o top_opt
vsim top_opt

Implicit vopt:
vsim my_top -voptargs="+acc"

Obviously, this will slow the simulation down compared to the fully
optimised design.
You can control what is 'accessible' (object types / modules /
instances etc) by adding more options to the vopt command (see the
User Manual for details) if you want to balance debug vs. performance.

Hope this helps

- Nigel
 
Thanks Nigel,

I was try that, but I'm still not able to see any changes of signals i
instantiated modules(in wave form window).

When I put some signals from instantiated verilog modules to wave for
window, after I hit "run" simulation those signals remain X.

Do you have any idea why is that so?

Best Regards

---------------------------------------
This message was sent using the comp.arch.fpga web interface o
http://www.FPGARelated.com
 
melinda wrote:

Is there a way of viewing the internal signals declared in the instantiated
verilog modules in Modelsim in wave window?
Click to expand...
add wave -r /*
 
Hi Melinda,

Can we assume that you are adding the internal signals with
some GUI commands like this:
View - Workspace - browse for your entitiy - Right Click - Add - Add to Wave

Brad Smallridge
AiVision

"melinda" <melinda.mel3@gmail.com> wrote in message
news:Soudna7GPeTPo23XnZ2dnUVZ_vWdnZ2d@giganews.com...
Hi all,

I am simulating a entity with Modelsim (v6.5c). Modelsim
only displays the input/output signals of the simulated top entity.

When I run simulation Modelsim displays only changes of input/output
signals of the top entity verilog module i.e. testbench (in objects window
i.e. in wave window), but nothing happening with signals declared in the
instantiated verilog modules.
(PS: In Cadence SimVision, I know that I was able to see changes of all
signals in testbench and also in instantiated verilog modules, in wave
window)

Is there a way of viewing the internal signals declared in the
instantiated
verilog modules in Modelsim in wave window?

Thanks very much

Regards
Click to expand...
 
On Nov 3, 12:28 pm, "melinda" <melinda.m...@gmail.com> wrote:
Thanks Nigel,

I was try that, but I'm still not able to see any changes of signals in
instantiated modules(in wave form window).

When I put some signals from instantiated verilog modules to wave form
window, after I hit "run" simulation those signals remain X.

Do you have any idea why is that so?

Best Regards      

---------------------------------------        
This message was sent using the comp.arch.fpga web interface onhttp://www..FPGARelated.com
Click to expand...
There are two things that happen in wave windows when you add signals,
first the signal is added to the wave viewer, but at the same time it
is added to the log. Normally in the wave view the signal will appear
as a total blank ("No Data") up to the point in the simulation where
you added it to the wave window. After that as you continue to run
the
sim it is filled in with the current state. If you want to be able
to add signals to the wave and see their full history, you should
add everything to the log when you start the simulation:

add log -r /*

Regards,
Gabor
 
If you can see the signals you want in the Objects window and can add
them to the Wave window then you've sorted any optimization
accessibility issues.

The fact that you're seeing X on signals simply reflects the value
Modelsim has calculated for them.
You're into plain old circuit debug activity now !

As others have suggested, log all the signals in your design with
log -r /*
run the simulation and then back/forward trace signals to see where
the X is introduced.
The Dataflow window is very useful for this.

- Nigel


Hi,
Click to expand...

When I said that I see X on signals... lets me explain you on example:
Suppose we have counter.v and counter_tb.v in our design. (counter_tb.
instantiates counter.v)
I add all signals from counter.v from objects window to wave window.
Then also add all signals from counter_tb.v objects window to wave window.
What I can see is all signal changes from counter_tb.v, including counte
instance signals from counter_tb.v.
With signals (in wave window) from counter.v nothing happening thoug
counter_tb.v instantiate counter.v module ????

Do you know how to see that signals in instantianed modules in wav
window.
(i.e. if we have clock signal in tesbench(counter_tb.v) which maps to cloc
signal in counter.v
I can see clock signal from testbench toogling but nothing happens wit
clock signal in counter.v (in wave window))

(PS: all mapping-signal orders etc... is just fine, just cant see what
describe above)

Bets regards

---------------------------------------
This message was sent using the comp.arch.fpga web interface o
http://www.FPGARelated.com
 
On Nov 3, 5:28 pm, "melinda" <melinda.m...@gmail.com> wrote:
Thanks Nigel,

I was try that, but I'm still not able to see any changes of signals in
instantiated modules(in wave form window).

When I put some signals from instantiated verilog modules to wave form
window, after I hit "run" simulation those signals remain X.

Do you have any idea why is that so?

Best Regards      

---------------------------------------        
This message was sent using the comp.arch.fpga web interface onhttp://www..FPGARelated.com
Click to expand...
If you can see the signals you want in the Objects window and can add
them to the Wave window then you've sorted any optimization
accessibility issues.

The fact that you're seeing X on signals simply reflects the value
Modelsim has calculated for them.
You're into plain old circuit debug activity now !

As others have suggested, log all the signals in your design with
log -r /*
run the simulation and then back/forward trace signals to see where
the X is introduced.
The Dataflow window is very useful for this.

- Nigel
 
On Nov 4, 10:38 am, "melinda" <melinda.m...@gmail.com> wrote:
If you can see the signals you want in the Objects window and can add
them to the Wave window then you've sorted any optimization
accessibility issues.

The fact that you're seeing X on signals simply reflects the value
Modelsim has calculated for them.
You're into plain old circuit debug activity now !

As others have suggested, log all the signals in your design with
log -r /*
run the simulation and then back/forward trace signals to see where
the X is introduced.
The Dataflow window is very useful for this.

- Nigel

Hi,

When I said that I see X on signals... lets me explain you on example:
Suppose we have counter.v and counter_tb.v in our design. (counter_tb.v
instantiates counter.v)  
I add all signals from counter.v from objects window to wave window.
Then also add all signals from counter_tb.v objects window to wave window..
What I can see is all signal changes from counter_tb.v, including counter
instance signals from counter_tb.v.
With signals (in wave window) from counter.v nothing happening though
counter_tb.v instantiate counter.v module ????

Do you know how to see that signals in instantianed modules in wave
window.
(i.e. if we have clock signal in tesbench(counter_tb.v) which maps to clock
signal in counter.v
I can see clock signal from testbench toogling but nothing happens with
clock signal in counter.v (in wave window))

(PS: all mapping-signal orders etc... is just fine, just cant see what I
describe above)

Bets regards      

---------------------------------------        
This message was sent using the comp.arch.fpga web interface onhttp://www..FPGARelated.com- Hide quoted text -

- Show quoted text -
Click to expand...
It sounds like you are seeing the instantianed module signal values,
it's just they aren't what you expect !
If you see a value for a signal in the Wave window then you are
logging it correctly.
Use the 'drivers' command to check correct connectivity

eg drivers /counter_tb/i_cnt/clk
will show where the clk signal in the instance i_cnt is driven from -
hopefully from code in counter_tb

Can you post any code we can look at?
Otherwise contact your local Mentor support team who can look at this
in more detail.

- Nigel
 
hello,

did u get an answer for this?
I also have the same issue.I am using ModelSim PE Student Edition 10.2c.I am not able to see the changes in instantiated module
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top