Modelsim System Verilog

[terabits]

Hi

Is there anyone using modelsim's questa for system verilog,
im not sure if it is the problem of questa or system verilog itself
but.....below code is not supported

clocking cd2 @(posedge busb.clk);
input #2 output #4ps busb.cmd;
input busb.enable; // this one to be specific...if input enb =
busb.enable it says unsupported but fine
endclocking

any one faced similar problem ?
is it compulsory that we need to use clocking blocks along with program
block only, i am seeing strange behaviour if i use it outside i mean
part of a interface, .......
please let me know where can i find errata about such problems with
system verilog !!!!


regards.