ModelSim Synchrnoizer

[Rob]

Hi,

I have a clock signal coming into my FPGA. It is a slow clock (10kHz)
that drives a state machine. I want to bring it into another clock
domain by using a 3 flops in a row like shift register. The clock
driving the sync flops is much faster (90MHz).

I am actually running a gate level simulation (Altera Cyclone 3).
ModelSim tells me I have timing violations on the first flop in the
synchronizer, which is to be expected. But the remaining flops in the
sync circuit will move this async signal into the new domain and should
eliminate metastablity and setup/hold violations. But when these timing
violations occur MS puts an unknown value at those positions which
affects all of the logic on the output of the synchronizer. Which in
turn screws up my state machine.

Can anyone offer up a suggestion on how to better setup MS under these
circumstances?

Thank you,
Rob

 

[Rob]

sorry, this was accidentally duplicate....

Rob wrote:

Hi,

I have a clock signal coming into my FPGA. It is a slow clock (10kHz)
that drives a state machine. I want to bring it into another clock
domain by using a 3 flops in a row like shift register. The clock
driving the sync flops is much faster (90MHz).

I am actually running a gate level simulation (Altera Cyclone 3).
ModelSim tells me I have timing violations on the first flop in the
synchronizer, which is to be expected. But the remaining flops in the
sync circuit will move this async signal into the new domain and should
eliminate metastablity and setup/hold violations. But when these timing
violations occur MS puts an unknown value at those positions which
affects all of the logic on the output of the synchronizer. Which in
turn screws up my state machine.

Can anyone offer up a suggestion on how to better setup MS under these
circumstances?

Thank you,
Rob

 

[Mike Treseler]

Rob wrote:

I am actually running a gate level simulation (Altera Cyclone 3).
ModelSim tells me I have timing violations on the first flop in the
synchronizer, which is to be expected. But the remaining flops in the
sync circuit will move this async signal into the new domain and should
eliminate metastablity and setup/hold violations.

I use one clock per entity.
In your case that would put the synchronizer in the fast entity.

Next I run static timing separately on each entity.
I just assume my synchronizer will work because it always has.
In any case, there is no way to prove it in simulation.

All I can do is calculate the MTBF for a synchronization failure.

For functional simulation, I synchronize the slow sim-clock.


-- Mike Treseler