Modelsim Slice error using numeric_std

[Beanut]

I'm having a problem in modelsim with what I think is legitimate VHDL.

I want to take the absolute value of a signed 15 bit std_logic_vector
and assign the 14 bit result using the numeric_std package. Since the
top bit should be empty I dont want to waste a register on it. The
following command compiles, and synthesizes perfectly in Syncplicity.

absin <= std_logic_vector(abs(signed(SinP2)))(13 downto 0);

When I try to simulate Modelsim complains:
# ** Error: Cannot slice the result of a type conversion.

Any ideas?

Thanks,
Beanut

 

[Duane Clark]

Beanut wrote:

I'm having a problem in modelsim with what I think is legitimate VHDL.

I want to take the absolute value of a signed 15 bit std_logic_vector
and assign the 14 bit result using the numeric_std package. Since the
top bit should be empty I dont want to waste a register on it...

Ignoring your actual question...

If the top bit doesn't go anywhere, then the mapping tools will strip it
out. So there will not be a "wasted" register. Take a look at a mapping
report file (in Xilinx that would be project.mrp).

 

[john Doef]

Beanut a écrit :

I'm having a problem in modelsim with what I think is legitimate VHDL.

I want to take the absolute value of a signed 15 bit std_logic_vector
and assign the 14 bit result using the numeric_std package. Since the
top bit should be empty I dont want to waste a register on it. The
following command compiles, and synthesizes perfectly in Syncplicity.

absin <= std_logic_vector(abs(signed(SinP2)))(13 downto 0);

When I try to simulate Modelsim complains:
# ** Error: Cannot slice the result of a type conversion.

Any ideas?
Modelsim is right: VHDL does not allow you to slice the result of a

type conversion.

You may either define and use a function (whose result can be sliced),
or make
absin 15 bits wide and ignore the MSB.

JD.

 

[Nicolas Matringe]

Maybe you could slice *before* the type conversion:
absin <= std_logic_vector(abs(signed(SinP2))(13 downto 0));

(untested, just an idea)

Nicolas

 

[Jonathan Bromley]

On 21 Sep 2005 14:43:48 -0700, "Beanut" <fourbeans@gmail.com> wrote:

I'm having a problem in modelsim with what I think is legitimate VHDL.

I want to take the absolute value of a signed 15 bit std_logic_vector
and assign the 14 bit result

The first problem is nothing to do with VHDL and everything to do
with twos-complement arithmetic: The result of abs() on a 15-bit
signed must be 15 bits wide, because the most-negative value
representable in 15 bits (-16384 decimal, 100_0000_0000_0000 binary)
needs 15 bits to represent its unsigned absolute value +16384.

If you can be 100% certain that the most negative value will never
occur (this may perhaps be true in some applications) then your
assumption that one MSB can be thrown away is correct. But you
need to be very careful. Assumptions that are true in design
have a nasty habit of becoming false on customer sites. It is
not obvious to me that the approximation obtained by 14-bit
truncation,
abs(-16384) ~= 0,
will be harmless in all applications.

following command compiles, and synthesizes perfectly in Syncplicity.
absin <= std_logic_vector(abs(signed(SinP2)))(13 downto 0);

It shouldn't. As ModelSim points out, you can't slice the
expression; you can only slice an array object. As others
have said, it would make sense to write a custom function
to do this operation. The same custom function could also
take special action if the most negative value appears -
for example, it could saturate abs(-16384) to +16383.
However, the extra logic required to do saturating-abs()
will almost certainly be larger than the single flip-flop
you are trying to save
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Beanut]

Thanks all. I forgot about the most negative number using all bits.
Although I won't need it, I at least understand why the return value is
the same size as the input.

My goal, in addition to saving space, was to have a warning free
synthesis, which is not possible when bits get mapped out, but I guess
that's what I'll do. I was suprised that synplicity didn't give a
signle error or warning.

Thanks for the education.