ModelSim + Simulink VHDL Cosimulation

[Patrick]

Hello everybody,

I would like to use Modelsim and Simulink to simulate my VHDL code...

But the minimum time step is 1 ns !!!

Is it possible to cosimulate VHDL with Simulink and have ŕ 1 ps time step ?

I tried also Simulink with ActiveHDL and I have the same problem !!!

Is it Simulink which have this limitation ?

Thanks to all VHDL designer...

 

[kiran]

"Patrick" <patrick.melet@dmradiocom.fr> wrote in message
news:54b3002.0410190149.7a37e1e@posting.google.com...

Hello everybody,

I would like to use Modelsim and Simulink to simulate my VHDL code...

But the minimum time step is 1 ns !!!

Is it possible to cosimulate VHDL with Simulink and have ŕ 1 ps time step
?

I tried also Simulink with ActiveHDL and I have the same problem !!!

Is it Simulink which have this limitation ?

Thanks to all VHDL designer...

Please see the section "Representation of Simulation Time" in Link for
ModelSim documentation
http://www.mathworks.com/access/helpdesk/help/toolbox/modelsim/

as mentioned in the doc there is a one to one correspondence between
simulink and modelsim simulation times.

1sec in simulink corresponds to 1tick in modelsim and the correspondence
holds irrespective of size of the tick which is modelsim resolution limit.

you can use the modelsim command "report simulator state" to verify your
current resolution limit and can change modelsim resolution limit using -t
option to 'vsimulink' or 'vsim'

vsimulink -t 1ps work.entity