ModelSim & Signal Spy

[Dan NITA]

Hello,

Please, someone can tell me if the ModelSim Signal Spy work on the post
route timing simulation?

Thanks,

Dan.

 

[Ajeetha]

AFAIK it does - you may have some escaped names that may cause some
trouble - can you show what problem you face?

Ajeetha
www.noveldv.com

 

[Dan NITA]

"Ajeetha" <ajeetha@gmail.com> a écrit dans le message

AFAIK it does - you may have some escaped names that may cause some
trouble - can you show what problem you face?

Ajeetha
www.noveldv.com

Thanks,

Is always the same old problem when all signals name disappear on the post
route timing simulation.

I prefer to use Altera FPGA's and Quartus because the post-fitting registers
are more legible and vectors don't split up.

Now I'm very interested by the Lattice XP family on a very complex design
with a 80MHz clock processor with double port memory, registers, pipelining
and a lot of peripherals.

Because getting maximum MIPS is crucial, each instruction is time-variable.
For example a jump will take 3 clocks, a read or write from memory 4 clocks,
and a 16-bit multiplication will need 6 clocks.

After synthesis, the estimated frequency is only 27.4MHz, because I don't
now how "to inform" the synthesizer that I'll wait 6 clock until the
multiplication is done.

This means that timing report is useless for me and I need to "see" what
happened inside the FPGA.

I hope I was clear enough.
Dan.

 

[Mike Treseler]

Dan NITA wrote:

After synthesis, the estimated frequency is only 27.4MHz, because I don't
now how "to inform" the synthesizer that I'll wait 6 clock until the
multiplication is done.

One way is to describe a synchronous strobe
that clock enables the output registers after
6 ticks.

-- Mike Treseler

 

[Dan NITA]

"Mike Treseler" <mike_treseler@comcast.net> a écrit dans le message> Dan NITA wrote:

After synthesis, the estimated frequency is only 27.4MHz, because I don't
now how "to inform" the synthesizer that I'll wait 6 clock until the
multiplication is done.

One way is to describe a synchronous strobe
that clock enables the output registers after
6 ticks.

-- Mike Treseler

Here is my actual code. Please, Can you confirm that "sigEndInstruction" do the clock enables like you say?





-- reset

if (RST = '1') then



----




elsif (rising_edge(CLK)) then



----



if (sigEndInstruction = '1') then



sigEndInstruction <= '0' after kHoldTime;



-- Test OpCode

case sigProgramDRD(15 downto 10) is



-- Load Data

when "000001" =>

sigAccumulator <= sigRamDRD after kHoldTime;



-- Add

when "000011" =>

sigAccumulator <= sigAddSubResult after kHoldTime;

sigRegAddSubOverflow <= sigAddSubOverflow after kHoldTime;



-- Sub

when "000100" =>

sigAccumulator <= sigAddSubResult after kHoldTime;

sigRegAddSubOverflow <= sigAddSubOverflow after kHoldTime;



-- Mult

when "000101" =>

sigAccumulator <= sigMultResult after kHoldTime;



----------



end case;



end if;

---------------



end if;

 

[Mike Treseler]

Dan NITA wrote:

Here is my actual code. Please, Can you confirm that “sigEndInstruction”
do the clock enables like you say?

No, *after* is ignored for synthesis.
I would decode a 3 bit counter.

-- Mike Treseler

 

[Dan NITA]

"Mike Treseler" <mike_treseler@comcast.net> a écrit dans le message> Dan
NITA wrote:

No, *after* is ignored for synthesis.
I would decode a 3 bit counter.

-- Mike Treseler

Oh no! I forget to say that ŤsigEndInstruction ť is set 1 clock after the
instruction counter carry is set.



I use “after” statement only for functional simulation purpose.



I think that the best way to test this idea, is to start a new shorten
project.



Dan.