ModelSim RGB Singal -> Image ?

M

Michael Schmid

Guest
Hi,

i am doing some VGA Output in ModelSym.
My vhdl Creats a R, G, B, vSynv, hSync and Blank.
The Waveform Output of the Testbench looks nice, but actually doesn't
mean anything to me.

Is there any way to make a nice looking Image (bmp, jpg, ..) out of the
Singals?

Thanks in Advice.
 
Michael Schmid <swimpy_pinball@yahoo.comSPAM> wrote:

i am doing some VGA Output in ModelSym.
My vhdl Creats a R, G, B, vSynv, hSync and Blank.
The Waveform Output of the Testbench looks nice, but actually doesn't
mean anything to me.

Is there any way to make a nice looking Image (bmp, jpg, ..) out of the
Singals?
if you have a prototyp board, then you can just program it and plug-in a
VGA monitor, like I've done: http://www.jroller.com/page/fb

The VGA input is connected with a resistor to the FPGA output, see
http://www.xilinx.com/products/spartan3/boards/s3_board_sch.pdf , page 7. I
think this is very clever, but it gives you only 8 colors, but for testing
this is enough.

--
Frank Buß, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
 
On 24 Jul 2004 07:40:33 -0700, "Tom Verbeure" <hombre@gmail.com>
wrote:

i am doing some VGA Output in ModelSym.
My vhdl Creats a R, G, B, vSynv, hSync and Blank.
The Waveform Output of the Testbench looks nice, but actually doesn't

mean anything to me.

Is there any way to make a nice looking Image (bmp, jpg, ..) out of
the
Singals?

What I'd do, is write out the RGB,VS,HS,B signals to a text file and
write a separate program in Perl, Python, C, whatever you feel like, to
analyze this text file and create the image. Another possibility would
be to program this directly in VHDL, but for the other languages, there
exist external (free) libraries that support image formats...
The full version of Modelsim supports Tcl/Tk, so it is possible to
capture the video to a memory inside the VHDL testbench, then use Tk
calls to display the image in a window, refreshing every time there is
an edge on Vsync (to give a "real time" display).

Regards,
Allan.
 
On Mon, 26 Jul 2004 13:46:24 +1000, Allan Herriman
<allan.herriman.hates.spam@ctam.com.au.invalid> wrote:

i am doing some VGA Output in ModelSym.
My vhdl Creats a R, G, B, vSynv, hSync and Blank.
The Waveform Output of the Testbench looks nice, but actually doesn't
mean anything to me.

Is there any way to make a nice looking Image (bmp, jpg, ..)

The full version of Modelsim supports Tcl/Tk, so it is possible to
capture the video to a memory inside the VHDL testbench, then use Tk
calls to display the image in a window, refreshing every time there is
an edge on Vsync (to give a "real time" display).
True, but Tcl is way sloooow for scribbling pixels. You would do
far better to write out a file in .ppm or some similar format,
and use the Tcl "image create photo" command to display it.

There are some useful Tcl extensions for handling various
kinds of image file, but .ppm is handled natively within
Tcl/Tk and is a pretty simple format.

It is also a VERY good idea to modify your VHDL code so that
the image is a lot smaller, when doing your early simulations.
It can take a painfully long time to simulate the generation
of several fields of full-size VGA image...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 

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