Modelsim $readmemh problem

Hi, dear community!
Doing some exersises with Quartus and Modelsim, I have got some strange behavior of readmemh function:

When I read the file whithin the testbench like that:

module Testbench2
#(parameter input_width = 16)
();
logic clk, reset;
logic [input_width-1:0] a,b;
logic [input_width-1:0] y, yexpected;
logic overflow, ofexpected;
logic [31:0] vectornum, errors;
logic [input_width*3:0] testvectors[10000:0];
// instantiate under test
sum_prefix dut({a,1'b0} ,{b,1'b0},y,overflow);
// generate clock
always
begin
clk=1; #5; clk=0; #5;
end
// at start, load vectors and pulse reset
initial
begin
$readmemh("../../Excercises/test2.tv",testvectors);
vectornum = 0; errors = 0;
reset = 1; #27; reset=0;
end
// apply test vectors on rising edge of clk
always@(posedge clk)
begin
#1; {a[input_width-1:0],b[input_width-1:0],yexpected[input_width-1:0],ofexpected}=testvectors[vectornum];
end
....
//blablabla

and test2.tv is like that

f001_0001_f002_0
f001_0fff_0000_1

it reads testvectors as
10010001f0020
10010fff00001

i.e. reads the first 4'hF as 4'h1. I tried both upper- and lower cases, no change.
BUT when I use readmemb and sinilar input file but boolean version it works perfect...
Modelsim SE version 10.4 64bit windows

 

[GaborSzakacs]

artemhvostov@gmail.com wrote:

Hi, dear community!
Doing some exersises with Quartus and Modelsim, I have got some strange behavior of readmemh function:

When I read the file whithin the testbench like that:

module Testbench2
#(parameter input_width = 16)
();
logic clk, reset;
logic [input_width-1:0] a,b;
logic [input_width-1:0] y, yexpected;
logic overflow, ofexpected;
logic [31:0] vectornum, errors;
logic [input_width*3:0] testvectors[10000:0];
// instantiate under test
sum_prefix dut({a,1'b0} ,{b,1'b0},y,overflow);
// generate clock
always
begin
clk=1; #5; clk=0; #5;
end
// at start, load vectors and pulse reset
initial
begin
$readmemh("../../Excercises/test2.tv",testvectors);
vectornum = 0; errors = 0;
reset = 1; #27; reset=0;
end
// apply test vectors on rising edge of clk
always@(posedge clk)
begin
#1; {a[input_width-1:0],b[input_width-1:0],yexpected[input_width-1:0],ofexpected}=testvectors[vectornum];
end
....
//blablabla

and test2.tv is like that

f001_0001_f002_0
f001_0fff_0000_1

it reads testvectors as
10010001f0020
10010fff00001

i.e. reads the first 4'hF as 4'h1. I tried both upper- and lower cases, no change.
BUT when I use readmemb and sinilar input file but boolean version it works perfect...
Modelsim SE version 10.4 64bit windows

You have:

parameter input_width = 16
logic [input_width*3:0] testvectors[10000:0];

so each testvectors word has 49 bits (bits are [48:0]).

f001_0001_f002_0 has 13 hex characters or 52 bits

So what you see in Modelsim is exactly what is to be expected.

--
Gabor