Modelsim: Operator overloading

J

JJ

Guest
Hi,
I am currently writing a test bench that contains a signal assignment within
a sequential process,

a<= b;

'a' is never assigned the value b during the run. I have several packages
included in this bench. I suspect operator overloading occuring. Can/does
Modelsim (the IDE I am using) have the capability to detect this is
happening? Or does anyone know a good way to trace or eliminate this
possibility?

Thanks
 
"JJ" <her@her.com> wrote in message
news:Owrzc.1519$Pt.1071@newssvr19.news.prodigy.com...
Hi,
I am currently writing a test bench that contains a signal assignment
within
a sequential process,

a<= b;

'a' is never assigned the value b during the run. I have several packages
included in this bench. I suspect operator overloading occuring. Can/does
Click to expand...
The assignment operator can not be overloaded.

My first quess would be that signal a is untentionally multiple driven (from
different processes). Since you use ModelSim you can use the command:
drivers a <return>
to find the driver for signal a.

Egbert Molenkamp
 
"Egbert Molenkamp" <remove_funny_molenkam@cs.utwente.nl> writes:

"JJ" <her@her.com> wrote in message
news:Owrzc.1519$Pt.1071@newssvr19.news.prodigy.com...
Hi,
I am currently writing a test bench that contains a signal assignment
within
a sequential process,

a<= b;

'a' is never assigned the value b during the run. I have several packages
included in this bench. I suspect operator overloading occuring. Can/does

The assignment operator can not be overloaded.

My first quess would be that signal a is untentionally multiple driven (from
different processes). Since you use ModelSim you can use the command:
drivers a <return
to find the driver for signal a.

Egbert Molenkamp
Click to expand...
As usual, Egbert's advice is good, but I would also put a breakpoint at the
beginning of your sequential process and see if the process sensitivity list or
other IF/THEN code is not working the way you expect it to by single stepping
through the process.

Note too that a signal with no driver will be a 'U' but a signal with multiple
drivers will likely be an 'X'.
 
I ended up calling Modelsim - I had upgraded to 5.8c from 5.5(something),
the advice was "Always blow away your work directory and start again when
you upgrade" - Guess what? Worked like a charm...

I'm not going crazy after all!


"JJ" <her@her.com> wrote in message
news:Owrzc.1519$Pt.1071@newssvr19.news.prodigy.com...
Hi,
I am currently writing a test bench that contains a signal assignment
within
a sequential process,

a<= b;

'a' is never assigned the value b during the run. I have several packages
included in this bench. I suspect operator overloading occuring. Can/does
Modelsim (the IDE I am using) have the capability to detect this is
happening? Or does anyone know a good way to trace or eliminate this
possibility?

Thanks
Click to expand...
 
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