Modelsim: No default binding for component

[Jimmy]

Hi, all ,

When simulating the behavioral model, it is ok, but when I simulating the
post-translate vhdl model, the simulation can't generate valid results
(output are all uncertain state U). from the warning, it seems the
UnitUnderTest has not been affiliated, Could you help explain what happens ?
thx,

** Warning: [1] top_rxfrontend_TB.vhd(143): No default binding for component
'top_rxfrontend'. (Generic 'bitwidth' is not on the entity.) --> actaully I
do have this on the entity.

# ** Warning: (vsim-3473) Component 'uut' is not bound.

best regards,
Jimmy

 

[Duane Clark]

Jimmy wrote:

Hi, all ,

When simulating the behavioral model, it is ok, but when I simulating the
post-translate vhdl model, the simulation can't generate valid results
(output are all uncertain state U). from the warning, it seems the
UnitUnderTest has not been affiliated, Could you help explain what happens ?
thx,

** Warning: [1] top_rxfrontend_TB.vhd(143): No default binding for component
'top_rxfrontend'. (Generic 'bitwidth' is not on the entity.) --> actaully I
do have this on the entity.

If I understand what you are saying, then the problem is that your
testbench is setting that generic, but the generic does not exist on the
post-translate (I assume post-synthesis?) model.

That would be expected; generics are resolved at synthesis time, and do
not appear in the post synthesis models. Take a look at the generated file.

--
My real email is akamail.com@dclark (or something like that).

 

[Jimmy]

Hi, Duane Clark ,
Yes, thx , as you expected, in the post-synthesis file, the generic
declaration is resolved, but in the testbench file , I use the same
testbench file with behavioul simulation (with generic declaration ). so in
post-synthesis simulation, UUT is not binding. Thanks for your help.
best regards,
Jimmy

"Duane Clark" <junkmail@junkmail.com> wrote in message
news:ce0mvr0285o@news4.newsguy.com...

Jimmy wrote:
Hi, all ,

When simulating the behavioral model, it is ok, but when I simulating
the
post-translate vhdl model, the simulation can't generate valid results
(output are all uncertain state U). from the warning, it seems the
UnitUnderTest has not been affiliated, Could you help explain what
happens ?
thx,

** Warning: [1] top_rxfrontend_TB.vhd(143): No default binding for
component
'top_rxfrontend'. (Generic 'bitwidth' is not on the entity.) --
actaully I
do have this on the entity.


If I understand what you are saying, then the problem is that your
testbench is setting that generic, but the generic does not exist on the
post-translate (I assume post-synthesis?) model.

That would be expected; generics are resolved at synthesis time, and do
not appear in the post synthesis models. Take a look at the generated
file.

--
My real email is akamail.com@dclark (or something like that).

 

[Wong]

I think you don't have your software setting correctly.

"Jimmy" <mljiang@eee.hku.hk> wrote in message news:<ce0jvj$hh$1@hkueee5.eee.hku.hk>...

Hi, all ,

When simulating the behavioral model, it is ok, but when I simulating the
post-translate vhdl model, the simulation can't generate valid results
(output are all uncertain state U). from the warning, it seems the
UnitUnderTest has not been affiliated, Could you help explain what happens ?
thx,

** Warning: [1] top_rxfrontend_TB.vhd(143): No default binding for component
'top_rxfrontend'. (Generic 'bitwidth' is not on the entity.) --> actaully I
do have this on the entity.

# ** Warning: (vsim-3473) Component 'uut' is not bound.

best regards,
Jimmy