[MODELSIM] How to add signals to wave which is a child of th

[John Smith]

Hello:

So I have a separate modules foo (with signals: foo_a, foo_b, foo_c)
and have another module foo1 (with signals: foo_x, foo_y, foo_z) which
instantiates foo within its module.

Now when I run a test on foo1, on ModelSim, the signals I can see to
add are the foo_x, foo_y and foo_z only. How do I get to add foo_a,
foo_b and foo_c signals to the wave, so that I could see what's going
on inside. I'm guessing this has to be with the paths, need help!
Thanks!

 

[RCIngham]

Hello:

So I have a separate modules foo (with signals: foo_a, foo_b, foo_c)
and have another module foo1 (with signals: foo_x, foo_y, foo_z) which
instantiates foo within its module.

Now when I run a test on foo1, on ModelSim, the signals I can see to
add are the foo_x, foo_y and foo_z only. How do I get to add foo_a,
foo_b and foo_c signals to the wave, so that I could see what's going
on inside. I'm guessing this has to be with the paths, need help!
Thanks!

RTFM.

add wave foo_instance_name/foo*

Or select the signals from the navigator window that is probably in the to
left of the GUI display, by clicking [+] icons to expand the instantiate
modules.


---------------------------------------
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[RCIngham]

On Apr 18, 1:25=A0pm, "RCIngham"
robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
Hello:

So I have a separate modules foo (with signals: foo_a, foo_b, foo_c)
and have another module foo1 (with signals: foo_x, foo_y, foo_z) which
instantiates foo within its module.

Now when I run a test on foo1, on ModelSim, the signals I can see to
add are the foo_x, foo_y and foo_z only. How do I get to add foo_a,
foo_b and foo_c signals to the wave, so that I could see what's going
on inside. I'm guessing this has to be with the paths, need help!
Thanks!

RTFM.

add wave foo_instance_name/foo*

Or select the signals from the navigator window that is probably in th
t=
op
left of the GUI display, by clicking [+] icons to expand th
instantiated
modules.

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com

Also if you are running simulation (vsim) and then adding the waves,
ModelSim by default logs signals only in the top level. To see the
waveforms in entirety, you will have to log them before running the
simulation . My ideal sequence of operation would be

#compile the source files and the testbench
vcom <files to compile

#load the design
vsim -t ps work.toplevel

#log all the signals in the design. The /* mean anything under root /
root here is the top level design
log -r /*

#now run the design for specific time or forever
run 100ns

#OR
run -a

I usually do the 'add wave' commands before any 'run' commands.
This has the advantages of slightly increasing simulation speed, and savin
some disk space for the logging file.
The disadvantage is that if you suddenly realise you need to look at
particular signal that you hadn't added, you have to start the simulatio
again.


---------------------------------------
Posted through http://www.FPGARelated.com

 

[shyam]

On Apr 18, 1:25 pm, "RCIngham"
<robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:

Hello:

So I have a separate modules foo (with signals: foo_a, foo_b, foo_c)
and have another module foo1 (with signals: foo_x, foo_y, foo_z) which
instantiates foo within its module.

Now when I run a test on foo1, on ModelSim, the signals I can see to
add are the foo_x, foo_y and foo_z only. How do I get to add foo_a,
foo_b and foo_c signals to the wave, so that I could see what's going
on inside. I'm guessing this has to be with the paths, need help!
Thanks!

RTFM.

add wave foo_instance_name/foo*

Or select the signals from the navigator window that is probably in the top
left of the GUI display, by clicking [+] icons to expand the instantiated
modules.

---------------------------------------        
Posted throughhttp://www.FPGARelated.com

Also if you are running simulation (vsim) and then adding the waves,
ModelSim by default logs signals only in the top level. To see the
waveforms in entirety, you will have to log them before running the
simulation . My ideal sequence of operation would be

#compile the source files and the testbench
vcom <files to compile>

#load the design
vsim -t ps work.toplevel

#log all the signals in the design. The /* mean anything under root /
root here is the top level design
log -r /*

#now run the design for specific time or forever
run 100ns

#OR
run -a