ModelSim error on istances

[Pleg]

Hi everybody, I was playing a little with ModelSim (it's the first time I
use it), I was compiling an old file for a simple 32 bits ALU. I have
correctly compiled the "alu_cell.v", which is a single bit cell, and I need
32 istances of it in the "alu32.v". So I wrote

alu_cell cell[31:0] (.d(d), .g(g), .p(p), .a(a), .b(b), .c(c), .S(S));

and the compiler said "** Error: alu32.v(11): near "cell": expecting:
IDENT"

What does it mean? The syntax I used worked perfectly on a different
compiler (I don't remember which), why is it not working here?

Thanks,


Pleg

 

[Art Stamness]

You probably just need to enable Verilog-2001 capabilities in the
simulator.

The instantiaion you are doing has a range specifier, what the error is
telling you is that it doesnt' expect a range specifier, it only
expects to see an ident. See section A.4.1 of IEEE 1364-2001 LRM Module
instantiation, if you are feeling pedantic.

The code listed above is legal Verilog 2001.

-Art

 

[Pleg]

You probably just need to enable Verilog-2001 capabilities in the
simulator.

The code listed above is legal Verilog 2001.

Yes, that's what I thought, there is a "Use Verilog 2001" compile option,
but even with that checked it doesn't work!


Pleg

 

Instance arrays were actually added in the Verilog-1995 standard. It's
just that most tools didn't implement them until they started
implementing Verilog-2001 extensions. Perhaps ModelSim missed the
extensions that were added in the Verilog-1995 standard.

 

Hi, Pleg -

The problem is that "cell" is a Verilog-2001 keyword, added to support
Verilog-2001 configuration files (the proposal originated with
Cadence). Change the instance name to something like "u[31:0]" and you
should be fine.

The array of instance was added to Verilog-1995. As a member of the
Verilog-1995 Standards Group, I fought hard to make sure that that one
enhancement made it into the standard.

ModelSim runs Verilog-2001 by default (very nice) and it implemented
arrays of instance years ago. I have used Verilog arrays of instance in
my Verilog training labs for years. It kills me that most Verilog users
don't even know that it exists in the language (and it is much easier
to use and much better supported than the Verilog generate statement
for contiguous arrays of instances).

Shame on "s...@cadence .com" for disparaging another vendor's tool and
not checking the keyword list (especially a keyword that was added by a
Cadence proposal). you meanie, you!

Regards - Cliff Cummings
Verilog & SystemVerilog Guru
www.sunburst-design.com

 

Good catch, Cliff. I missed the keyword and made a wrong guess about
the problem.

You may recall that I argued that the config keywords should only be
reserved in separate config files, and not be reserved in Verilog
source. My concern was conflicts with commonly used identifiers, and
this question illustrates the problem (though in new code rather than
legacy code). Looking back at my statistics for the config keywords,
"cell" was the second most common offender, after "config".

Returning to the original question, the advice to make sure that
Verilog-2001 was turned on may have been exactly backward. If you turn
it off, then "cell" should no longer be a keyword. If this doesn't
also turn off instance arrays (which it shouldn't, if this doesn't also
turn off the Verilog-1995 extensions), then this should work. Of
course, you probably just want to change the name.

 

[Pleg]

The problem is that "cell" is a Verilog-2001 keyword, added to support
Verilog-2001 configuration files (the proposal originated with
Cadence). Change the instance name to something like "u[31:0]" and you
should be fine.

Ah! Thank you so much! I really couldn't understand it!

The array of instance was added to Verilog-1995. As a member of the
Verilog-1995 Standards Group, I fought hard to make sure that that one
enhancement made it into the standard.

ModelSim runs Verilog-2001 by default (very nice) and it implemented
arrays of instance years ago. I have used Verilog arrays of instance in
my Verilog training labs for years. It kills me that most Verilog users
don't even know that it exists in the language (and it is much easier
to use and much better supported than the Verilog generate statement
for contiguous arrays of instances).

Yeah I agree, it's incredibly useful


Pleg