ModelSim Error locally static expression

R

Rick North

Guest
Hi all,

ModelSim PE VHDL 6.0c warning
# ** Warning: sel.vhd: Case choice must be a locally static expression.

I have a package where the Event_Definition are stored they are all
equal lenght and of the same type.

But I get this "locally static expression" warning, which I think I
should not have, since the EventCH
does not change unless the package file changes. The lenght and type is
thus constant during the simulation.

I pasted a code snippet below. My goal is to use this design in several
systems which have different events.

So why the warning and what to to about it? Better way to write the
code?

Cheers,
Rick N


entity SelEvent is
generic (
system : systems := Bob);
port ( clk : in std_logic;
reset : in std_logic;
MyEnable : in std_logic;
EventCH : in unsigned(Event_definition(System)(Bob)'high
downto Event_definition(System)(Bob)'low);
MyEvent : out std_logic
);
end entity SelEvent;

process(clk, reset)
begin
if reset = '1' then
MyEvent <= '0';
elsif clk'event and clk = '1' then
case EventCh is
-- no warnings
-- when "000001" => MyEvent <= Phillips_Event and MyEnable;
-- when "000010" => MyEvent <= Pauls_Event and MyEnable;
-- when "000100" => MyEvent <= Peters_Event and MyEnable;
-- when "001000" => MyEvent <= Rays_Event and MyEnable;
-- when "010000" => MyEvent <= Sahras_Event and MyEnable;
-- when "100000" => MyEvent <= Bobs_Event and MyEnable;

-- warnings
when Event_definition(System)(Phillip) => MyEvent <=
Phillips_Event and MyEnable;
when Event_definition(System)(Paul) => MyEvent <=
Pauls_Event and MyEnable;
when Event_definition(System)(Ray) => MyEvent <= Rays_Event
and MyEnable;
when Event_definition(System)(Peter) => MyEvent <=
Peters_Event and MyEnable;
when Event_definition(System)(Sahra) => MyEvent <=
Sahras_Event and MyEnable;
when Event_definition(System)(Bob) => MyEvent <= Bobs_Event
and MyEnable;
when others => null;
-- translate off
assert false report "Error Selection for
MyEvent" severity note;
-- translate on
end case;
end if;
end process;
 
Rick North wrote:

But I get this "locally static expression" warning, which I think I
should not have, since the EventCH
does not change unless the package file changes.
The short answer is that's the way it is.
A case expression is limited to operands that are scalar
Use an if-elsif with your constant array.

The long answer is:
http://groups-beta.google.com/groups?q=Case+choice+locally+static+expression


-- Mike Treseler
 
Hi Rick,
two things, that might help...
1) your definitions have to be in the package declaration, not the
body, to be locally static.
2) your definitions have to be constants. That is, they can not be
computed via some function, even though the parameters of the functions
are constants. That is because the actual call to the function takes
place after compile time and thus is not locally static.

I hope that helps...
Cheers,
Andreas Jahn
 
ajahn wrote:

2) your definitions have to be constants. That is, they can not be
computed via some function, even though the parameters of the functions
are constants. That is because the actual call to the function takes
place after compile time and thus is not locally static.
An element of a constant array out as well.

-- Mike Treseler

entity case_expr is
end entity case_expr;
-- Mon Jul 25 10:54:15 2005 M. Treseler
architecture sim of case_expr is
-- demo of constant array element in a case expr
begin
demo : process is
constant what_int_c : natural := 42;
type four_ints_t is array(0 to 3) of natural;
constant these_ints_c : four_ints_t :=(11, 13, 17, 19);
begin -- demo
case what_int_c is
when 11 =>
when these_ints_c(2) =>
-- "Warning: Case choice must be a locally static expression"
when others =>
end case;

wait;
end process demo;
end architecture sim;
 
Thank you all for clearing up the mess. I will change my case to an
priority decoder.

Cheers,
R N

Mike Treseler skrev:
ajahn wrote:

2) your definitions have to be constants. That is, they can not be
computed via some function, even though the parameters of the functions
are constants. That is because the actual call to the function takes
place after compile time and thus is not locally static.

An element of a constant array out as well.

-- Mike Treseler

entity case_expr is
end entity case_expr;
-- Mon Jul 25 10:54:15 2005 M. Treseler
architecture sim of case_expr is
-- demo of constant array element in a case expr
begin
demo : process is
constant what_int_c : natural := 42;
type four_ints_t is array(0 to 3) of natural;
constant these_ints_c : four_ints_t :=(11, 13, 17, 19);
begin -- demo
case what_int_c is
when 11 =
when these_ints_c(2) =
-- "Warning: Case choice must be a locally static expression"
when others =
end case;

wait;
end process demo;
end architecture sim;
 
Rick North wrote:
Thank you all for clearing up the mess. I will change my case to an
priority decoder.
You are welcome.
Note that the if-elsif statement
requires overlapping cases to
imply priority.

-- Mike Treseler
 
Ahh.. Then I didn't mean priority. Each statement has only one
result in my case.

I do want to generate a structure of if-elsif where the number of elsif
can be the same as the number of Event_definitions and end with an else
which has an assertion for non valid Event.

Best Regards,
RN



Mike Treseler skrev:
Rick North wrote:
Thank you all for clearing up the mess. I will change my case to an
priority decoder.

You are welcome.
Note that the if-elsif statement
requires overlapping cases to
imply priority.

-- Mike Treseler
 
Ahh.. Then I didn't mean priority. Each statement has only one
result in my case.

I do want to generate a structure of if-elsif where the number of elsif
can be the same as the number of Event_definitions and end with an else
which has an assertion for non valid Event.

Best Regards,
RN



Mike Treseler skrev:
Rick North wrote:
Thank you all for clearing up the mess. I will change my case to an
priority decoder.

You are welcome.
Note that the if-elsif statement
requires overlapping cases to
imply priority.

-- Mike Treseler
 
Hi Rick,

VHDL is rather picky when it comes to case statements.
Locally static more or less means that the value should
be constant within the context of the primary unit.

For example, 'systems' (a local generic) is locally static,
but not globally static(because someone can override the
generic during an instantiation of SelEvent.

Now, there are two things that are not locally defined in
you case items : 'Event_definition' and the values 'Bob' ..'Sahra' etc.
I assume tha 'Event_definition' is a constant in a package,
and 'Bob' ..'Sahra' etc are enumeration values.
Since these are not declared locally, they are not locally static.
Therefor the message.

Now, they are constants, so there is no question what there value is.
ModelSim CAN figure out their value, and thus has no problem
simulating your model. But just for the sake of the LRM rule,
they issue a warning.

So, not much to worry about.

An educated guess how this came about : ModelSim is really good in
checking all VHDL LRM rules, so probably had an error for this one.
Synthesis tools however traditionally did not check the strict
LRM local/global static rules so rigorously (as long as it is
constant, its OK), and thus ModelSim probably was fed-up with the
complaints that "this-and-that tool handles this fine, why do you error out ?"
and downgraded the message to a warning...

Rob

"Rick North" <dontreplytothisaddy@hotmail.com> wrote in message news:1122301200.126958.279770@g47g2000cwa.googlegroups.com...
Hi all,

ModelSim PE VHDL 6.0c warning
# ** Warning: sel.vhd: Case choice must be a locally static expression.

I have a package where the Event_Definition are stored they are all
equal lenght and of the same type.

But I get this "locally static expression" warning, which I think I
should not have, since the EventCH
does not change unless the package file changes. The lenght and type is
thus constant during the simulation.

I pasted a code snippet below. My goal is to use this design in several
systems which have different events.

So why the warning and what to to about it? Better way to write the
code?

Cheers,
Rick N


entity SelEvent is
generic (
system : systems := Bob);
port ( clk : in std_logic;
reset : in std_logic;
MyEnable : in std_logic;
EventCH : in unsigned(Event_definition(System)(Bob)'high
downto Event_definition(System)(Bob)'low);
MyEvent : out std_logic
);
end entity SelEvent;

process(clk, reset)
begin
if reset = '1' then
MyEvent <= '0';
elsif clk'event and clk = '1' then
case EventCh is
-- no warnings
-- when "000001" => MyEvent <= Phillips_Event and MyEnable;
-- when "000010" => MyEvent <= Pauls_Event and MyEnable;
-- when "000100" => MyEvent <= Peters_Event and MyEnable;
-- when "001000" => MyEvent <= Rays_Event and MyEnable;
-- when "010000" => MyEvent <= Sahras_Event and MyEnable;
-- when "100000" => MyEvent <= Bobs_Event and MyEnable;

-- warnings
when Event_definition(System)(Phillip) => MyEvent <=
Phillips_Event and MyEnable;
when Event_definition(System)(Paul) => MyEvent <=
Pauls_Event and MyEnable;
when Event_definition(System)(Ray) => MyEvent <= Rays_Event
and MyEnable;
when Event_definition(System)(Peter) => MyEvent <=
Peters_Event and MyEnable;
when Event_definition(System)(Sahra) => MyEvent <=
Sahras_Event and MyEnable;
when Event_definition(System)(Bob) => MyEvent <= Bobs_Event
and MyEnable;
when others => null;
-- translate off
assert false report "Error Selection for
MyEvent" severity note;
-- translate on
end case;
end if;
end process;
 
Hi Rob,

Thank you for your explanation! Yes ModelSim is picky, but I like
picky:) That is why I pursued why ModelSim was giving me a warning but
my synthesis tool gladly accepted the code.

But what was the reason for the LRM rule in the first place? There must
be an errorus condition which the rule is used for protecting sloppy
engineers, as my self, from generating some ugly hardware. If not then
the rule is obsolete or invalid or need an exception. Never the less, I
am glad that ModelSim is picky about the compliance of the LRM.

Cheers,
/R N
 
Hi Rob,

Thank you for your explanation! Yes ModelSim is picky, but I like
picky:) That is why I pursued why ModelSim was giving me a warning but
my synthesis tool gladly accepted the code.

But what was the reason for the LRM rule in the first place? There must
be an errorus condition which the rule is used for protecting sloppy
engineers, as my self, from generating some ugly hardware. If not then
the rule is obsolete or invalid or need an exception. Never the less, I
am glad that ModelSim is picky about the compliance of the LRM.

Cheers,
/R N
 

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