ModelSim # Error loading design

M

mBird

Guest
I just downloaded Xilinx ISE 8.1 and ModelSim XE III/Starter 6.0d
I make a simple project, using schematic (one and gate) an dthen make a test
bench waveform. I then do Simulate Behaviural Model but no matter what I do
I always get # Error loading design with no other indication of erors. In
the previous version of ISE and ModelSim it all worked so I am not sure what
is error?
Any help greatly appretiared!

The results of from ModelSim:
# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl
# do m.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE III vlog 6.0d Compiler 2005.04 Apr 26 2005
# -- Compiling module FD_MXILINX_matt_sch
# -- Compiling module matt_sch
#
# Top level modules:
# matt_sch
# Model Technology ModelSim XE III vcom 6.0d Compiler 2005.04 Apr 26 2005
# -- Loading package standard
# -- Loading package textio
# -- Loading package std_logic_1164
# -- Loading package std_logic_textio
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity m
# -- Compiling architecture testbench_arch of m
# Model Technology ModelSim XE III vlog 6.0d Compiler 2005.04 Apr 26 2005
# -- Compiling module glbl
#
# Top level modules:
# glbl
# vsim -L cpld_ver -L uni9000_ver -lib work -t 1ps m glbl
# Loading C:\Modeltech_xe_starter\win32xoem/../std.standard
# Loading C:\Modeltech_xe_starter\win32xoem/../std.textio(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body)
# Loading work.m(testbench_arch)
# XE version supports only a single HDL
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./m.fdo PAUSED at line 8
 
Looks like you are using both vlog (verilog) and vcom (vhdl) compiler, check
that you have a dual language license,

Hans.
www.ht-lab.com

"mBird" <no@email.com> wrote in message
news:11uo5ck9o574tfa@corp.supernews.com...
I just downloaded Xilinx ISE 8.1 and ModelSim XE III/Starter 6.0d
I make a simple project, using schematic (one and gate) an dthen make a
test bench waveform. I then do Simulate Behaviural Model but no matter
what I do I always get # Error loading design with no other indication of
erors. In the previous version of ISE and ModelSim it all worked so I am
not sure what is error?
Any help greatly appretiared!

The results of from ModelSim:
# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl
# do m.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE III vlog 6.0d Compiler 2005.04 Apr 26 2005
# -- Compiling module FD_MXILINX_matt_sch
# -- Compiling module matt_sch
#
# Top level modules:
# matt_sch
# Model Technology ModelSim XE III vcom 6.0d Compiler 2005.04 Apr 26 2005
# -- Loading package standard
# -- Loading package textio
# -- Loading package std_logic_1164
# -- Loading package std_logic_textio
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity m
# -- Compiling architecture testbench_arch of m
# Model Technology ModelSim XE III vlog 6.0d Compiler 2005.04 Apr 26 2005
# -- Compiling module glbl
#
# Top level modules:
# glbl
# vsim -L cpld_ver -L uni9000_ver -lib work -t 1ps m glbl
# Loading C:\Modeltech_xe_starter\win32xoem/../std.standard
# Loading C:\Modeltech_xe_starter\win32xoem/../std.textio(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body)
# Loading work.m(testbench_arch)
# XE version supports only a single HDL
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./m.fdo PAUSED at line 8
Click to expand...
 
I downloaded the Xilinx ISE 8.1 and ModelSim XE III/Starter 6.0d from Xilinx
site. These are the free starter products. In the past I used ISE and
ModelSim older versions and all worked. I am not sure what I should do to
make these work. I just want simple VHDL and to use Schematics. I dont see
any way to tell ISE not to do dual language? Any advice appretiated!

"Hans" <hans64@ht-lab.com> wrote in message
news:e6YGf.23547$Fy4.22367@newsfe4-win.ntli.net...
Looks like you are using both vlog (verilog) and vcom (vhdl) compiler,
check that you have a dual language license,

Hans.
www.ht-lab.com

"mBird" <no@email.com> wrote in message
news:11uo5ck9o574tfa@corp.supernews.com...
I just downloaded Xilinx ISE 8.1 and ModelSim XE III/Starter 6.0d
I make a simple project, using schematic (one and gate) an dthen make a
test bench waveform. I then do Simulate Behaviural Model but no matter
what I do I always get # Error loading design with no other indication of
erors. In the previous version of ISE and ModelSim it all worked so I am
not sure what is error?
Any help greatly appretiared!

The results of from ModelSim:
# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl
# do m.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE III vlog 6.0d Compiler 2005.04 Apr 26 2005
# -- Compiling module FD_MXILINX_matt_sch
# -- Compiling module matt_sch
#
# Top level modules:
# matt_sch
# Model Technology ModelSim XE III vcom 6.0d Compiler 2005.04 Apr 26 2005
# -- Loading package standard
# -- Loading package textio
# -- Loading package std_logic_1164
# -- Loading package std_logic_textio
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity m
# -- Compiling architecture testbench_arch of m
# Model Technology ModelSim XE III vlog 6.0d Compiler 2005.04 Apr 26 2005
# -- Compiling module glbl
#
# Top level modules:
# glbl
# vsim -L cpld_ver -L uni9000_ver -lib work -t 1ps m glbl
# Loading C:\Modeltech_xe_starter\win32xoem/../std.standard
# Loading C:\Modeltech_xe_starter\win32xoem/../std.textio(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body)
# Loading work.m(testbench_arch)
# XE version supports only a single HDL
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./m.fdo PAUSED at line 8
Click to expand...
 
You are referencing Verilog primitive libraries on the vsim line:

vsim -L cpld_ver -L uni9000_ver -lib

There must be an option in ISE to select the VHDL or Verilog? Are your
schematics translated to Verilog?

Hans
www.ht-lab.com


"mBird" <no@email.com> wrote in message
news:11up72iddd8ao91@corp.supernews.com...
I downloaded the Xilinx ISE 8.1 and ModelSim XE III/Starter 6.0d from
Xilinx site. These are the free starter products. In the past I used ISE
and ModelSim older versions and all worked. I am not sure what I should do
to make these work. I just want simple VHDL and to use Schematics. I dont
see any way to tell ISE not to do dual language? Any advice appretiated!

"Hans" <hans64@ht-lab.com> wrote in message
news:e6YGf.23547$Fy4.22367@newsfe4-win.ntli.net...
Looks like you are using both vlog (verilog) and vcom (vhdl) compiler,
check that you have a dual language license,

Hans.
www.ht-lab.com

"mBird" <no@email.com> wrote in message
news:11uo5ck9o574tfa@corp.supernews.com...
I just downloaded Xilinx ISE 8.1 and ModelSim XE III/Starter 6.0d
I make a simple project, using schematic (one and gate) an dthen make a
test bench waveform. I then do Simulate Behaviural Model but no matter
what I do I always get # Error loading design with no other indication
of erors. In the previous version of ISE and ModelSim it all worked so I
am not sure what is error?
Any help greatly appretiared!

The results of from ModelSim:
# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl
# do m.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE III vlog 6.0d Compiler 2005.04 Apr 26
2005
# -- Compiling module FD_MXILINX_matt_sch
# -- Compiling module matt_sch
#
# Top level modules:
# matt_sch
# Model Technology ModelSim XE III vcom 6.0d Compiler 2005.04 Apr 26
2005
# -- Loading package standard
# -- Loading package textio
# -- Loading package std_logic_1164
# -- Loading package std_logic_textio
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity m
# -- Compiling architecture testbench_arch of m
# Model Technology ModelSim XE III vlog 6.0d Compiler 2005.04 Apr 26
2005
# -- Compiling module glbl
#
# Top level modules:
# glbl
# vsim -L cpld_ver -L uni9000_ver -lib work -t 1ps m glbl
# Loading C:\Modeltech_xe_starter\win32xoem/../std.standard
# Loading C:\Modeltech_xe_starter\win32xoem/../std.textio(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body)
# Loading work.m(testbench_arch)
# XE version supports only a single HDL
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./m.fdo PAUSED at line 8
Click to expand...
 
Hi
this problem arises when u r openning two instances of the model sim.
try this out and see did u open the two instances of the modelsim.
"XE version supports only a single HDL " this error is common when two
windows of modelsim wre open

Bye

Vips
 
The project Synthesis Tool setting has only one setting: XST (VHDL/Verilog)
I did get it to work by selecting ModelSim (PS/SE) Mixed instead of ModelSim
XE as the project's simulator but I am puzzled as to how that could even
work since I have ModelSim XE installed only?
Thanks for your help and info!

"Hans" <hans64@ht-lab.com> wrote in message
news:rw1Hf.24458$Fy4.9903@newsfe4-win.ntli.net...
You are referencing Verilog primitive libraries on the vsim line:

vsim -L cpld_ver -L uni9000_ver -lib

There must be an option in ISE to select the VHDL or Verilog? Are your
schematics translated to Verilog?

Hans
www.ht-lab.com


"mBird" <no@email.com> wrote in message
news:11up72iddd8ao91@corp.supernews.com...
I downloaded the Xilinx ISE 8.1 and ModelSim XE III/Starter 6.0d from
Xilinx site. These are the free starter products. In the past I used ISE
and ModelSim older versions and all worked. I am not sure what I should do
to make these work. I just want simple VHDL and to use Schematics. I dont
see any way to tell ISE not to do dual language? Any advice appretiated!

"Hans" <hans64@ht-lab.com> wrote in message
news:e6YGf.23547$Fy4.22367@newsfe4-win.ntli.net...
Looks like you are using both vlog (verilog) and vcom (vhdl) compiler,
check that you have a dual language license,

Hans.
www.ht-lab.com

"mBird" <no@email.com> wrote in message
news:11uo5ck9o574tfa@corp.supernews.com...
I just downloaded Xilinx ISE 8.1 and ModelSim XE III/Starter 6.0d
I make a simple project, using schematic (one and gate) an dthen make a
test bench waveform. I then do Simulate Behaviural Model but no matter
what I do I always get # Error loading design with no other indication
of erors. In the previous version of ISE and ModelSim it all worked so
I am not sure what is error?
Any help greatly appretiared!

The results of from ModelSim:
# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl
# do m.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE III vlog 6.0d Compiler 2005.04 Apr 26
2005
# -- Compiling module FD_MXILINX_matt_sch
# -- Compiling module matt_sch
#
# Top level modules:
# matt_sch
# Model Technology ModelSim XE III vcom 6.0d Compiler 2005.04 Apr 26
2005
# -- Loading package standard
# -- Loading package textio
# -- Loading package std_logic_1164
# -- Loading package std_logic_textio
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity m
# -- Compiling architecture testbench_arch of m
# Model Technology ModelSim XE III vlog 6.0d Compiler 2005.04 Apr 26
2005
# -- Compiling module glbl
#
# Top level modules:
# glbl
# vsim -L cpld_ver -L uni9000_ver -lib work -t 1ps m glbl
# Loading C:\Modeltech_xe_starter\win32xoem/../std.standard
# Loading C:\Modeltech_xe_starter\win32xoem/../std.textio(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body)
# Loading work.m(testbench_arch)
# XE version supports only a single HDL
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./m.fdo PAUSED at line 8
Click to expand...
 
Hi --
Thanks for the idea. I am sure to have only one instance running.
I did get it to work by selecting ModelSim (PS/SE) Mixed instead of ModelSim
XE as the project's simulator but I am puzzled as to how that could even
work since I have ModelSim XE installed only?
Thanks for your help and info!

"VIPS" <thevipulsinha@gmail.com> wrote in message
news:1139583102.164399.197010@o13g2000cwo.googlegroups.com...
Hi
this problem arises when u r openning two instances of the model sim.
try this out and see did u open the two instances of the modelsim.
"XE version supports only a single HDL " this error is common when two
windows of modelsim wre open

Bye

Vips
Click to expand...
 
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