ModelSim control

[Kev P. (AKA Niv)]

How do I "flow control" modlsim?
I want to invoke modelsim (I'm using HDL designer, so invoked from
there at the moment), and then modelsim must ask for a user input to
select which path of the test bench to go down.

I can do OK by editing a value in the test bench, but that fixes the
flow between each edit.

I want "user control" the flow from the start of modelsim.

TIA, Niv.

 

[Jonathan Bromley]

On 3 Aug 2005 05:24:04 -0700, "Kev P. (AKA Niv)"
<kev.parsons@mbda.co.uk> wrote:

How do I "flow control" modlsim?
I want to invoke modelsim (I'm using HDL designer, so invoked from
there at the moment), and then modelsim must ask for a user input to
select which path of the test bench to go down.

I can do OK by editing a value in the test bench, but that fixes the
flow between each edit.

(1)
Easy, but gives a crummy user interface: Get your VHDL test bench to
read user data from the predefined TEXT input file INPUT. For
example, to read an integer:

use std.textio.all;
...
variable L: line;
variable N: integer;
...
write(L, string'("Enter an integer")); -- create prompt string
writeline(output, L); -- emit prompt string
readline(input, L); -- get a line of user input
read(L, N); -- extract user's integer

(2)
Slightly more tricky, but potentially gives very much better
user interaction: Get ModelSim's Tcl (and perhaps Tk) interpreter
to obtain the user input as part of a ModelSim Tcl script ("do"
script, in ModelSim jargon). Later in that same script, use the
user's input value to control some aspect of the simulation -
for example, you could force a value on to an undriven signal
in the test bench; or you could load the simulation with
a top-level generic set to the user-supplied value (see the
detailed help on ModelSim's [vsim] command); or you could
get Tcl to write a text file that is later read in by the
VHDL test bench. (This is probably the very best way to do it.)
Your Tcl script can be supplied as part of the ModelSim
invocation line using the -do option. You'll need to check the
HDL Designer documentation to see how to configure that, since
you are launching ModelSim from HDL Designer rather than from
the operating system command line.

Here's a little Tcl/Tk example that may help you start. Suppose
your VHDL test bench reads its control data from a file in the
simulator's working directory, and this file has the fixed name
"sim_control.txt". This Tcl script will bring up a file selector
dialog box allowing the user to choose any file; it then copies
the chosen file to "sim_control.txt", and then runs the
simulation. Check on the Tcl/Tk documentation on [tk_getOpenFile]
for many options that you can use to control the file selector
dialog box: starting directory, filename filters, etc.

# Tcl/Tk script to plug a text file into the simulation
#
# Bring up file selector dialog box for user to choose.
# Capture the chosen file name into variable "chosen_file".
set chosen_file [tk_getOpenFile -title "Choose Sim Control File"]
#
# Make sure user didn't cancel out of the selector dialog.
if {[string length $chosen_file]==0} {
tk_messageBox \
-type ok \
-message "No file chosen" \
-title "Aborting due to user error"
exit
}
#
# OK, if we got this far we have chosen a file.
# Make sure it's a ".txt" file.
if {![string equal [file extension $chosen_file] .txt]} {
tk_messageBox \
-type ok \
-message "Control file must have .txt extension" \
-title "Aborting due to user error"
exit
}
#
# OK, we have a .txt file. Copy it to where VHDL can see it.
file copy $chosen_file sim_control.txt
#
# Finally, load and launch the ModelSim simulation.
vsim SomeTopLevelModule
add wave -r /*
run -all


HTH
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Mike Treseler]

Kev P. (AKA Niv) wrote:

I want to invoke modelsim
and then modelsim must ask for a user input to
select which path of the test bench to go down.
I can do OK by editing a value in the test bench, but that fixes the
flow between each edit.

I do something similar to Jonathan's excellent tcl example.
Instead of a text file, I control the testbench flow with
generic constants passed using the vsim -G option.
I keep some example command lines as comments
at the top of my testbench. This way I have the
choice of just pasting the commands to a shell
from my editor, or making a tcl/tk script
to select and play back one of the commands from the
modelsim gui.

-- Mike Treseler

 

[Jonathan Bromley]

On Wed, 03 Aug 2005 14:28:22 +0100, Jonathan Bromley
<jonathan.bromley@doulos.com> wrote:

Kevin,

Here's a little Tcl/Tk example that may help you start.

It will be less helpful than it should, because it
contains an error :-(

# OK, we have a .txt file. Copy it to where VHDL can see it.
file copy $chosen_file sim_control.txt

Whoops, that should have been

file copy -force $chosen_file sim_control.txt
^^^^^^

so that the copy works even when sim_control.txt already
exists in the working directory (which, of course, it
probably will).
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Kev P. (AKA Niv)]

OK, I'va managed to control the ModelSim flow by invoking a "do" macro,
which
sets a signal in the test bench called "sim_time" as follows:

force -deposit sim:/proto_test_tb/i1/sim_time 1 0

However, this still means I have to edit the .do file, I really want
ModelSim
to ask the user to type in something like a "Y" or "N" response to
cause the
appropriate branch control.

Kev P.

 

[Jonathan Bromley]

On 8 Aug 2005 03:14:24 -0700, "Kev P. (AKA Niv)"
<kev.parsons@mbda.co.uk> wrote:

OK, I'va managed to control the ModelSim flow by invoking a "do" macro,
which
sets a signal in the test bench called "sim_time" as follows:

force -deposit sim:/proto_test_tb/i1/sim_time 1 0

However, this still means I have to edit the .do file, I really want
ModelSim
to ask the user to type in something like a "Y" or "N" response to
cause the
appropriate branch control.

hi again Kevin,

see my original response; the key question here is where you
want the user interaction to take place. It can be done either
from within VHDL itself, or from the Tcl "do" script.
Getting user input from VHDL is easy enough, and it makes your
code completely portable across different simulation
environments, but the user interface will be rubbish.
Getting user input from Tcl is probably even easier, but you
then have to work out how to get that input to influence the
simulation - as Mike Treseler pointed out, you could use it
to patch up some generics, or you could use a force command
to put the appropriate value on to a signal that's otherwise
floating in your testbench.

Anyways, for what it's worth here's the "user Y/N" thing,
worked through in detail for both VHDL and Tcl.

In VHDL, it's easiest to add a little procedure to your
test bench. THe procedure is sufficiently useful that
it's probably worth putting into a package, along with
any other string manipulation utilities that you create.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
use std.textio.all;
....
procedure UserYN(
prompt: in string;
yes : out boolean
) is

variable L, user: line;
variable response: character;
variable OK: boolean;
variable dontknow: boolean := true;
begin
-- first prompt is polite
write (L, prompt & " Enter Y/N");
writeline (output, L);
while dontknow loop
-- get user input
readline(input, user);
read(user, response, OK);
if OK then -- there was at least one char on the line
case response is
when 'Y' | 'y' => yes := true; dontknow := false;
when 'N' | 'n' => yes := false; dontknow := false;
when others =>
write(L, prompt & " Bad input: use Y=yes, N=no");
end case;
else -- user gave us a blank line!
write(L, prompt & " Please enter SOMETHING");
end if; -- if OK
-- spit out second, stroppier prompt
writeline(output, L);
end loop; -- while dontknow
-- Get rid of any storage still in use for line "user"
deallocate(user);
end;

Now you can just call the procedure with a suitable prompt:

signal green: std_logic;
....
process Test_Control is
variable Choice: boolean;
begin
UserYN("Do you want it green?", Choice);
if Choice then
green <= '1';
else
green <= '0';
end if;
wait;
end process;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

In Tcl it's easy, too...

# Display prompt; push the partial line of text to the console
puts -nonewline "Do you want it green (enter Y/N)? "
flush stdout
# Loop until we have satisfactory input
set dontknow 1
while {$dontknow} {
# Read user input into a variable
gets stdin user_line
# Check user input - only the first character
switch -- [string index $user_line 0] {
y -
Y {
set dontknow 0
set yes 1
}
n -
N {
set dontknow 0
set yes 0
}
default {
puts -nonewline "Try again: Green (Y/N)? "
flush stdout
}
}
}

# use the result - yes is either 1 or 0
force -deposit sim:/tb_top/green $yes

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Even more fun can be had by adding a GUI using Tcl/Tk, but
we'll save that for another day...

HTH
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Kev P. (AKA Niv)]

Thanks a lot Jonathan, I really should have figured out the VHDL
myself,
having seen your answer, it's pretty obvious now.

I'll have a go with the tcl as well;
thanks again, Kev P,