Modelsim compile problem

A

Andreas

Guest
Hi!

I'm trying to compile som auto generated vhdl code. The vhdl-file with
my entity and architecture also contains a package declaration. When I
try to compile this, it complains that the package (that is declared
at the top of the file) is not found (when it's needed futher down in
the file.)

The vhdl-code is autogenerated, and the best solution would be if
there is a way to inform the compler how to deal with this wia the
..fdo-file or other parameters.

The code looks like this (but with correct "new line"). The first
lines declares the package and the _last_ line uses the package.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package myReadBuffer_types is
type std_logic_vector_7d0_array_69d0 is array
(69 downto 0) of std_logic_vector(7 downto 0);

type unsigned_7d0_array_69d0 is array (69 downto 0)
of unsigned(7 downto 0);
end;

library ieee;
use ieee.std_logic_1164.all;
use work.artbuilderpack_numeric.all;
use work.myReadBuffer_types.all;
use ieee.numeric_std.all;

entity myReadBuffer is
port (
pixel_addr: in std_logic_vector(31 downto 0);
pixel_out: out std_logic_vector(31 downto 0)
);
end myReadBuffer;

architecture rtl of myReadBuffer is
begin
COMPUTE_PROC: process(
pixel_addr
)
variable pixel_addr_n1: unsigned(31 downto 0);
variable pixel_out_n1: unsigned(31 downto 0);
variable imageData: unsigned_7d0_array_69d0;
....


My .fdo-file starts like this:

vlib work
vcom -just e -93 -explicit artbuilderpack_numeric.vhd
vcom -skip e -93 -explicit artbuilderpack_numeric.vhd
vcom -just e -93 -explicit design.vhd
vcom -skip e -93 -explicit design.vhd


And generates this error output:

# ** Error: (vcom-11) Could not find work.myreadbuffer_types.
# ** Error: design.vhd(77): cannot find expanded name:
work.myreadbuffer_types
# ** Error: design.vhd(77): Unknown field: myreadbuffer_types.
# ** Error: design.vhd(80): VHDL Compiler exiting
# ERROR: /home/lundgren/.caddata/modelsim/modeltech/bin/../linux/vcom
failed.
# Error in macro ./ReadBuffer.fdo line 4

Anyone have an idea???

Thanks in advance,
Andreas Lundgren - Holland
 
Hi Andreas,

Your -just arguments are incorrect, try this:
vcom -just p -93 -explicit artbuilderpack_numeric.vhd
vcom -just b -93 -explicit artbuilderpack_numeric.vhd
vcom -just e -93 -explicit design.vhd
vcom -just a -93 -explicit design.vhd

Regards,
Hans.
www.ht-lab.com


"Andreas" <d99alu@efd.lth.se> wrote in message
news:f7cd4365.0402050225.36d95e9e@posting.google.com...
Hi!

I'm trying to compile som auto generated vhdl code. The vhdl-file with
my entity and architecture also contains a package declaration. When I
try to compile this, it complains that the package (that is declared
at the top of the file) is not found (when it's needed futher down in
the file.)

The vhdl-code is autogenerated, and the best solution would be if
there is a way to inform the compler how to deal with this wia the
.fdo-file or other parameters.

The code looks like this (but with correct "new line"). The first
lines declares the package and the _last_ line uses the package.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package myReadBuffer_types is
type std_logic_vector_7d0_array_69d0 is array
(69 downto 0) of std_logic_vector(7 downto 0);

type unsigned_7d0_array_69d0 is array (69 downto 0)
of unsigned(7 downto 0);
end;

library ieee;
use ieee.std_logic_1164.all;
use work.artbuilderpack_numeric.all;
use work.myReadBuffer_types.all;
use ieee.numeric_std.all;

entity myReadBuffer is
port (
pixel_addr: in std_logic_vector(31 downto 0);
pixel_out: out std_logic_vector(31 downto 0)
);
end myReadBuffer;

architecture rtl of myReadBuffer is
begin
COMPUTE_PROC: process(
pixel_addr
)
variable pixel_addr_n1: unsigned(31 downto 0);
variable pixel_out_n1: unsigned(31 downto 0);
variable imageData: unsigned_7d0_array_69d0;
...


My .fdo-file starts like this:

vlib work
vcom -just e -93 -explicit artbuilderpack_numeric.vhd
vcom -skip e -93 -explicit artbuilderpack_numeric.vhd
vcom -just e -93 -explicit design.vhd
vcom -skip e -93 -explicit design.vhd


And generates this error output:

# ** Error: (vcom-11) Could not find work.myreadbuffer_types.
# ** Error: design.vhd(77): cannot find expanded name:
work.myreadbuffer_types
# ** Error: design.vhd(77): Unknown field: myreadbuffer_types.
# ** Error: design.vhd(80): VHDL Compiler exiting
# ERROR: /home/lundgren/.caddata/modelsim/modeltech/bin/../linux/vcom
failed.
# Error in macro ./ReadBuffer.fdo line 4

Anyone have an idea???

Thanks in advance,
Andreas Lundgren - Holland
 

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