P
Pasacco
Guest
Hi
I need following help with MODELSIM
How to do "C + TCL + Verilog" simulation.
Verilog code contains following statement.
------------------------------------------
initial $benchC(1, "Tcl", filename);
------------------------------------------
'benchC' is written by C code.
When I simulate the module, following warning is encountered.
------------------------------------------
* Warning: (vsim-PLI-3003) /opt/data/RTL/testbench.v(123): [TOFD] -
System task or function '$benchC' is not defined.
------------------------------------------
My question is that
How can we compile (or call) C codes and simulate, together with
Verilog codes.
If will be grateful if someone point me out any well-described
document (for beginner) about
------------------------------------------
How to do simulation "C + Verilog" or "C + VHDL"
and
How to do simulation 'TCL'
------------------------------------------
Thank you in advance
I need following help with MODELSIM
How to do "C + TCL + Verilog" simulation.
Verilog code contains following statement.
------------------------------------------
initial $benchC(1, "Tcl", filename);
------------------------------------------
'benchC' is written by C code.
When I simulate the module, following warning is encountered.
------------------------------------------
* Warning: (vsim-PLI-3003) /opt/data/RTL/testbench.v(123): [TOFD] -
System task or function '$benchC' is not defined.
------------------------------------------
My question is that
How can we compile (or call) C codes and simulate, together with
Verilog codes.
If will be grateful if someone point me out any well-described
document (for beginner) about
------------------------------------------
How to do simulation "C + Verilog" or "C + VHDL"
and
How to do simulation 'TCL'
------------------------------------------
Thank you in advance